Masami Nakajima

According to our database, Masami Nakajima authored at least 17 papers between 1993 and 2016.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2016

A 20uA/MHz at 200MHz microcontroller with low power memory access scheme for small sensing nodes.

Masami Nakajima, Ichiro Naka, Fumihiro Matsushima, Tadaaki Yamauchi

Proceedings of the 2016 IEEE Symposium in Low-Power and High-Speed Chips, 2016

2011

A Scalable Massively Parallel Processor for Real-Time Image Processing.

Takashi Kurafuji, Masaru Haraguchi, Masami Nakajima, Tetsu Nishijima, Tetsushi Tanizaki, Hiroyuki Yamasaki, Takeaki Sugimura, Yuta Imai, Masakatsu Ishizaki, Takeshi Kumaki, Kan Murata, Kanako Yoshida, Eisuke Shimomura, Hideyuki Noda, Yoshihiro Okuno, Shunsuke Kamijo, Tetsushi Koide, Hans Jürgen Mattausch, Kazutami Arimoto

IEEE J. Solid State Circuits, 2011

Implementation and evaluation of FAST corner detection on the massively parallel embedded processor MX-G.

Yushi Moko, Yoshihiro Watanabe, Takashi Komuro, Masatoshi Ishikawa, Masami Nakajima, Kazutami Arimoto

Proceedings of the IEEE Conference on Computer Vision and Pattern Recognition, 2011

2010

A scalable massively parallel processor for real-time image processing.

Takashi Kurafuji, Masaru Haraguchi, Masami Nakajima, Takayuki Gyohten, Tetsu Nishijima, Hiroyuki Yamasaki, Yuta Imai, Masakatsu Ishizaki, Takeshi Kumaki, Yoshihiro Okuno, Tetsushi Koide, Hans Jürgen Mattausch, Kazutami Arimoto

Proceedings of the IEEE International Solid-State Circuits Conference, 2010

2009

Heterogeneous Multicore SoC With SiP for Secure Multimedia Applications.

Hiroyuki Kondo, Sugako Otani, Masami Nakajima, Osamu Yamamoto, Norio Masui, Naoto Okumura, Mamoru Sakugawa, Masaya Kitao, Koichi Ishimi, Masayuki Sato, Fumitaka Fukuzawa, Satoshi Imasu, Nobuhiro Kinoshita, Yusuke Ota, Kazutami Arimoto, Toru Shimizu

IEEE J. Solid State Circuits, 2009

2008

Design and Implementation of a Configurable Heterogeneous Multicore SoC With Nine CPUs and Two Matrix Processors.

Hiroyuki Kondo, Masami Nakajima, Norio Masui, Sugako Otani, Naoto Okumura, Yukari Takata, Takashi Nasu, Hirokazu Takata, Takashi Higuchi, Mamoru Sakugawa, Hayato Fujiwara, Kazuya Ishida, Koichi Ishimi, Satoshi Kaneko, Teruyuki Itoh, Masayuki Sato, Osamu Yamamoto, Kazutami Arimoto

IEEE J. Solid State Circuits, 2008

Heterogeneous multicore SoC for secure multimedia applications.

Hiroyuki Kondo, Masami Nakajima, Sugako Otani, Osamu Yamamoto, Norio Masui, Naoto Okumura, Mamoru Sakugawa, Masaya Kitao, Koichi Ishimi, Masayuki Sato, Fumitaka Fukuzawa, Kazuhiro Inaoka, Yoshihiro Saito, Kazutami Arimoto, Toru Shimizu

Proceedings of the IEEE 2008 Custom Integrated Circuits Conference, 2008

2007

The Circuits and Robust Design Methodology of the Massively Parallel Processor Based on the Matrix Architecture.

Hideyuki Noda, Tetsushi Tanizaki, Takayuki Gyohten, Katsumi Dosaka, Masami Nakajima, Katsuya Mizumoto, Kanako Yoshida, Takenobu Iwao, Tetsu Nishijima, Yoshihiro Okuno, Kazutami Arimoto

IEEE J. Solid State Circuits, 2007

The Design and Implementation of the Massively Parallel Processor Based on the Matrix Architecture.

Hideyuki Noda, Masami Nakajima, Katsumi Dosaka, Kiyoshi Nakata, Motoki Higashida, Osamu Yamamoto, Katsuya Mizumoto, Tetsushi Tanizaki, Takayuki Gyohten, Yoshihiro Okuno, Hiroyuki Kondo, Yukihiko Shimazu, Kazutami Arimoto, Kazunori Saito, Toru Shimizu

IEEE J. Solid State Circuits, 2007

Design of a Processing Element Based on Quaternary Differential Logic for a Multi-Core SIMD Processor.

Hirokatsu Shirahama, Akira Mochizuki, Takahiro Hanyu, Masami Nakajima, Kazutami Arimoto

Proceedings of the 37th International Symposium on Multiple-Valued Logic, 2007

2006

Design and Evaluation of a Massively Parallel Processor Based on Matrix Architecture.

Toru Shimizu, Masami Nakajima, Masahiro Kainaga

IEICE Trans. Electron., 2006

A 40GOPS 250mW massively parallel processor based on matrix architecture.

Masami Nakajima, Hideyuki Noda, Katsumi Dosaka, Kiyoshi Nakata, Motoki Higashida, Osamu Yamamoto, Katsuya Mizumoto, Hiroyuki Kondo, Yukihiko Shimazu, Kazutami Arimoto, Kazunori Saitoh, Toru Shimizu

Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006

2005

Implementation of Face Recognition Processing Using an Embedded Processor.

Hiroyuki Kondo, Masami Nakajima, Miroslaw Bober, Krzysztof Kucharski, Osamu Yamamoto, Toru Shimizu

J. Robotics Mechatronics, 2005

2004

A 600-MHz single-chip multiprocessor with 4.8-GB/s internal shared pipelined bus and 512-kB internal memory.

Satoshi Kaneko, Hiroyuki Kondo, Norio Masui, Koichi Ishimi, Teruyuki Itou, Masayuki Satou, Naoto Okumura, Yukari Takata, Hirokazu Takata, Mamoru Sakugawa, Takashi Higuchi, Sugako Ohtani, Kei Sakamoto, Naoshi Ishikawa, Masami Nakajima, Shunichi Iwata, Kiyoshi Hayase, Satoshi Nakano, Sachiko Nakazawa, Kunihiro Yamada, Toru Shimizu

IEEE J. Solid State Circuits, 2004

1996

Design of Highly Parallel Linear Digital Circuits Based on Symbol-Level Redundancy.

Masami Nakajima, Michitaka Kameyama

Proceedings of the 26th IEEE International Symposium on Multiple-Valued Logic, 1996

1994

Design of Multiple-Valued Linear Digital Circuits for Highly Parallel <i>k</i>-Ary Operations.

Masami Nakajima, Michitaka Kameyama

Proceedings of the 24th IEEE International Symposium on Multiple-Valued Logic, 1994

1993

Design of Multiple-Valued Linear Digital Circuits for Highly Parallel Unary Operations.

Masami Nakajima, Michitaka Kameyama

Proceedings of the 23rd IEEE International Symposium on Multiple-Valued Logic, 1993