Masako Ohta

According to our database, Masako Ohta authored at least 4 papers between 1989 and 2003.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2003

A 0.5-V power-supply scheme for low-power system LSIs using multi-V_th SOI CMOS technology.

Tsuneaki Fuse, Masako Ohta, Motoki Tokumasu, Hiroshige Fujii, Shigeru Kawanaka, Atsushi Kameyama

IEEE J. Solid State Circuits, 2003

2002

A new reduced clock-swing flip-flop: NAND-type keeper flip-flop (NDKFF).

Motoki Tokumasu, Hiroshige Fujii, Masako Ohta, Tsunealu Fuse, Atsushi Kameyama

Proceedings of the IEEE 2002 Custom Integrated Circuits Conference, 2002

1989

New nibbled-page architecture for high-density DRAMs.

Kenji Numata, Yukihito Oowaki, Yasuo Itoh, Takahiko Hara, Kenji Tsuchida, Masako Ohta, Shigyoshi Watanabe, Kazunori Ohuchi

IEEE J. Solid State Circuits, August, 1989

An experimental 16-Mbit CMOS DRAM chip with a 100-MHz serial read/write mode.

Shigeyoshi Watanabe, Yukihito Oowaki, Yasuo Itoh, Koji Sakui, Kenji Numata, Tsuneaki Fuse, Takayuki Kobayashi, Kenji Tsuchida, Masahiko Chiba, Takahiko Hara, Masako Ohta, Fumio Horiguchi, Katsuhiko Hieda, Akihiro Nitayama, Takeshi Hamamoto, Kazunori Ohuchi, Fujio Masuoka

IEEE J. Solid State Circuits, June, 1989