Masaki Kumanoya

According to our database, Masaki Kumanoya authored at least 7 papers between 1989 and 1999.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

1999

Source-synchronization and timing vernier techniques for 1.2-GB/s SLDRAM interface.

Yasunobu Nakase, Yoshikazu Morooka, David J. Perlman, Daniel J. Kolor, Jae-Myoung Choi, Hyun J. Shin, Tsutomu Yoshimura, Naoya Watanabe, Yoshio Matsuda, Masaki Kumanoya, Michihiro Yamada

IEEE J. Solid State Circuits, 1999

1996

A 90-MHz 16-Mb system integrated memory with direct interface to CPU.

Katsumi Dosaka, Akira Yamazaki, Naoya Watanabe, Hideaki Abe, Jun Ohtani, Toshiyuki Ogawa, Kazunori Ishihara, Masaki Kumanoya

IEEE J. Solid State Circuits, 1996

1995

Advances in DRAM interfaces.

Masaki Kumanoya, Toshiyuki Ogawa, Kazunari Inoue

IEEE Micro, 1995

1994

Testing 256k Word x 16 Bit Cache DRAM (CDRAM).

Yasuhiro Konishi, Toshiyuki Ogawa, Masaki Kumanoya

Proceedings of the Proceedings IEEE International Test Conference 1994, 1994

1992

A 100-MHz 4-Mb cache DRAM with fast copy-back scheme.

Katsumi Dosaka, Yasuhiro Konishi, Kouji Hayano, Katsumitsu Himukashi, Akira Yamazaki, Hisashi Iwamoto, Masaki Kumanoya, Hisanori Hamano, Tsutomu Yoshihara

IEEE J. Solid State Circuits, November, 1992

1990

A 38-ns 4-Mb DRAM with a battery-backup (BBU) mode.

Yasuhiro Konishi, Katsumi Dosaka, Takahiro Komatsu, Yoshinori Inoue, Masaki Kumanoya, Youichi Tobita, Hideki Genjyo, Masao Nagatomo, Tsutomu Yoshihara

IEEE J. Solid State Circuits, October, 1990

1989

Analysis of coupling noise between adjacent bit lines in megabit DRAMs.

Yasuhiro Konishi, Masaki Kumanoya, Hiroyuki Yamasaki, Katsumi Dosaka, Tsutomu Yoshihara

IEEE J. Solid State Circuits, February, 1989