Masakazu Yamashina

According to our database, Masakazu Yamashina authored at least 19 papers between 1994 and 2002.

Collaborative distances:

• Dijkstra number of three.
• Erdős number of four.

2002

Guest editorial.

Masakazu Yamashina, Shekhar Y. Borkar

IEEE J. Solid State Circuits, 2002

A low-power W-CDMA demodulator using specially-designed micro-DSPs.

Hiroyuki Igura, Masaru Hirata, Junya Yamada, Masakazu Yamashina, Shigeru Ono

Proceedings of the IEEE 2002 Custom Integrated Circuits Conference, 2002

2001

Guest editorial.

David B. Scott, Masakazu Yamashina

IEEE J. Solid State Circuits, 2001

2000

A Single-Chip Multiprocessor for Smart Terminals.

Masato Edahiro, Satoshi Matsushita, Masakazu Yamashina, Naoki Nishi

IEEE Micro, 2000

Spatial-temporal mapping of real applications on a Dynamically Reconfigurable Logic Engine (DRLE) LSI.

Koichiro Furuta, Taro Fujii, Masato Motomura, Kazutoshi Wakabayashi, Masakazu Yamashina

Proceedings of the IEEE 2000 Custom Integrated Circuits Conference, 2000

Reconfigurable computing: its concept and a practical embodiment using newly developed dynamically reconfigurable logic (DRL) LSI: invited talk.

Masakazu Yamashina, Masato Motomura

Proceedings of ASP-DAC 2000, 2000

1999

A 2000-MOPS embedded RISC processor with a Rambus DRAM controller.

Kazumasa Suzuki, Masayuki Daito, Tomoo Inoue, Kouhei Nadehara, Masahiro Nomura, Masayuki Mizuno, Tomofumi Iima, Shoichiro Sato, Terumi Fukuda, Tomohisa Arai, Ichiro Kuroda, Masakazu Yamashina

IEEE J. Solid State Circuits, 1999

1998

An 800-MOPS, 110-mW, 1.5-V, parallel DSP for mobile multimedia processing.

Hiroyuki Igura, Yukihiro Naito, Kenya Kazama, Ichiro Kuroda, Masato Motomura, Masakazu Yamashina

IEEE J. Solid State Circuits, 1998

An Embedded DRAM-FPGA Chip with Instantaneous Logic Reconfiguration.

Masato Motomura, Yoshiharu Aimoto, Atsufkni Shibayama, Yoshikazu Yabe, Masakazu Yamashina

Proceedings of the 6th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM '98), 1998

1997

A 1.5-W single-chip MPEG-2 MP@ML video encoder with low power motion estimation and clocking.

Masayuki Mizuno, Yasushi Ooi, Naoya Hayashi, Junichi Goto, Masatoshi Hozumi, Koichiro Furuta, Atsufumi Shibayama, Yoetsu Nakazawa, Osamu Ohnishi, Shu-Yu Zhu, Yutaka Yokoyama, Yoichi Katayama, Hideto Takano, Noriyuki Miki, Yuzo Senda, Ichiro Tamitani, Masakazu Yamashina

IEEE J. Solid State Circuits, 1997

A 0.25-μm CMOS 0.9-V 100-MHz DSP core.

Masanori Izumikawa, Hiroyuki Igura, Hitoshi Wakabayashi, Ken Nakajima, Tohru Mogami, Tadahiko Horiuchi, Masakazu Yamashina

IEEE J. Solid State Circuits, 1997

An MPEG-2 encoder architecture based on a single-chip dedicated LSI with a control MPU.

Yasushi Ooi, Osamu Ohnishi, Yutaka Yokoyama, Yoichi Katayama, Masayuki Mizuno, Masakazu Yamashina, Hideo Takano, Naoya Hayashi, Ichiro Tamitani

Proceedings of the 1997 IEEE International Conference on Acoustics, 1997

1996

Capacitance coupling immune, transient sensitive accelerator for resistive interconnect signals of subquarter micron ULSI.

Tomofumi lima, Masayuki Mizuno, Tadahiko Horiuchi, Masakazu Yamashina

IEEE J. Solid State Circuits, 1996

A GHz MOS adaptive pipeline technique using MOS current-mode logic.

Masayuki Mizuno, Masakazu Yamashina, Koichiro Furuta, Hiroyuki Igura, Hitoshi Abiko, Kazuhiro Okabe, Atsuki Ono, Hachiro Yamada

IEEE J. Solid State Circuits, 1996

A current direction sense technique for multiport SRAM's.

Masanori Izumikawa, Masakazu Yamashina

IEEE J. Solid State Circuits, 1996

1995

Design of 1.28-GB/s high bandwidth 2-Mb SRAM for integrated memory array processor applications.

Tohru Kimura, Kazuyuki Nakamura, Yoshiharu Aimoto, Takashi Manabe, Nobuyuki Yamashita, Yoshihiro Fujita, Shin'ichiro Okazaki, Masakazu Yamashina

IEEE J. Solid State Circuits, June, 1995

1994

A 500 MHz, 32 bit, 0.4 μm CMOS RISC processor.

Kazumasa Suzuki, Masakazu Yamashina, Takashi Nakayama, Masanori Izumikawa, Masahiro Nomura, Hiroyuki Igura, Hideki Heiuchi, Junichi Goto, Toshiaki Inoue, Youichi Koseki, Hitoshi Abiko, Kazuhiro Okabe, Atsuki Ono, Youich Yano, Hachiro Yamada

IEEE J. Solid State Circuits, December, 1994

A 3.84 GIPS integrated memory array processor with 64 processing elements and a 2-Mb SRAM.

Nobuyuki Yamashita, Tohru Kimura, Yoshihiro Fujita, Yoshiharu Aimoto, Takashi Manabe, Shin'ichiro Okazaki, Kazuyuki Nakamura, Masakazu Yamashina

IEEE J. Solid State Circuits, November, 1994

A 300-MHz 16-b 0.5-μm BiCMOS digital signal processor core LSI.

Masahiro Nomura, Masakazu Yamashina, Junichi Goto, Toshiaki Inoue, Kazumasa Suzuki, Masato Motomura, Youichi Koseki, Benjamin S. Shih, Tadahiko Horiuchi, Nobuhisa Hamatake, Kouichi Kumagai, Tadayoshi Enomoto, Hachiro Yamada

IEEE J. Solid State Circuits, March, 1994