Masakazu Aoki

According to our database1, Masakazu Aoki authored at least 21 papers between 1988 and 2008.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

1990
1995
2000
2005
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Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2008
Concise Modeling of Transistor Variations in an LSI Chip and Its Application to SRAM Cell Sensitivity Analysis.
IEICE Trans. Electron., 2008

2005
Design Guidelines and Process Quality Improvement for Treatment of Device Variations in an Lsi Chip.
IEICE Trans. Electron., 2005

Approach for physical design in sub-100 nm era.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Challenge: variability characterization and modeling for 65- to 90-nm processes.
Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005

1999
A precise on-chip voltage generator for a gigascale DRAM with a negative word-line scheme.
IEEE J. Solid State Circuits, 1999

1998
Dual-period self-refresh scheme for low-power DRAM's with on-chip PROM mode register.
IEEE J. Solid State Circuits, 1998

1995
Low-noise, high-speed data transmission using a ringing-canceling output buffer.
IEEE J. Solid State Circuits, December, 1995

An experimental 220-MHz 1-Gb DRAM with a distributed-column-control architecture.
IEEE J. Solid State Circuits, November, 1995

1994
Two-dimensional power-line selection scheme for low subthreshold-current multi-gigabit DRAM's.
IEEE J. Solid State Circuits, August, 1994

Subthreshold-current reduction circuits for multi-gigabit DRAM's.
IEEE J. Solid State Circuits, July, 1994

A charge recycle refresh for Gb-scale DRAM's in file applications.
IEEE J. Solid State Circuits, June, 1994

Sub-1-μA dynamic reference voltage generator for battery-operated DRAMs.
IEEE J. Solid State Circuits, April, 1994

1993
256-Mb DRAM circuit technologies for file applications.
IEEE J. Solid State Circuits, November, 1993

Subthreshold current reduction for decoded-driver by self-reverse biasing (DRAMs).
IEEE J. Solid State Circuits, November, 1993

A high-speed, small-area, threshold-voltage-mismatch compensation sense amplifier for gigabit-scale DRAM arrays.
IEEE J. Solid State Circuits, July, 1993

Sub-1-V swing internal bus architecture for future low-power ULSIs.
IEEE J. Solid State Circuits, April, 1993

A single 1.5-V digital chip for a 10<sup>6</sup> synapse neural network.
IEEE Trans. Neural Networks, 1993

1990
A tunable CMOS-DRAM voltage limiter with stabilized feedback amplifier.
IEEE J. Solid State Circuits, October, 1990

1989
A 1.5-V DRAM for battery-based applications.
IEEE J. Solid State Circuits, October, 1989

New DRAM noise generation under half-V<sub>cc</sub> precharge and its reduction using a transposed amplifier.
IEEE J. Solid State Circuits, August, 1989

1988
An experimental large-capacity semiconductor file memory using 16-levels/cell storage.
IEEE J. Solid State Circuits, February, 1988


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