Masakatsu Suda

According to our database, Masakatsu Suda authored at least 7 papers between 2002 and 2009.

Collaborative distances:

• Dijkstra number of six.
• Erdős number of five.

2009

Dynamic arbitrary jitter injection method for ≫6.5Gb/s SerDes testing.

Tasuku Fujibe, Masakatsu Suda, Kazuhiro Yamamoto, Yoshihito Nagata, Kazuhiro Fujita, Daisuke Watanabe, Toshiyuki Okayasu

Proceedings of the 2009 IEEE International Test Conference, 2009

2007

2GS/s, 10ps Resolution CMOS Differential Time-to-Digital Converter for Real-Time Testing of Source-Synchronous Memory Device.

Kazuhiro Yamamoto, Masakatsu Suda, Toshiyuki Okayasu

Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, 2007

2006

Multi Strobe Circuit for 2.133GHz Memory Test System.

Kazuhiro Yamamoto, Masakatsu Suda, Toshiyuki Okayasu, Hirokatsu Niijima, Koichi Tanaka

Proceedings of the 2006 IEEE International Test Conference, 2006

1.83ps-Resolution CMOS Dynamic Arbitrary Timing Generator for >4GHz ATE Applications.

Toshiyuki Okayasu, Masakatsu Suda, Kazuhiro Yamamoto, Shusuke Kantake, Satoshi Sudou, Daisuke Watanabe

Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006

2005

CMOS high-speed, high-precision timing generator for 4.266-Gbps memory test system.

Masakatsu Suda, Kazuhiro Yamamoto, Toshiyuki Okayasu, Shusuke Kantake, Satoshi Sudou, Daisuke Watanabe

Proceedings of the Proceedings 2005 IEEE International Test Conference, 2005

2004

34.1Gbps Low Jitter, Low BER High-Speed Parallel CMOS Interface for Interconnections in High-Speed Memory Test System.

Daisuke Watanabe, Masakatsu Suda, Toshiyuki Okayasu

Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004

2002

CMOS Circuit Technology for Precise GHz Timing Generator.

Toshiyuki Okayasu, Masakatsu Suda, Kazuhiro Yamamoto

Proceedings of the Proceedings IEEE International Test Conference 2002, 2002