Masaitsu Nakajima

According to our database, Masaitsu Nakajima authored at least 9 papers between 1989 and 2012.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2012

Session 18 overview: Innovative circuits in emerging technologies: Technology directions subcommittee.

Masaitsu Nakajima, Shekhar Borkar

Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012

Vision for future television.

Atsuki Inoue, Masaitsu Nakajima

Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012

2007

Low Power Techniques for Mobile Application SoCs Based on Integrated Platform "UniPhier".

Masaitsu Nakajima, Takao Yamamoto, Masayuki Yamasaki, Tetsu Hosoki, Masaya Sumita

Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007

1992

An 80-MFLOPS (peak) 64-b microprocessor for parallel computer.

Hiraku Nakano, Masaitsu Nakajima, Yasuhiro Nakakura, Tadahiro Yoshida, Yoshiyuki Goi, Yuji Nakai, Reiji Segawa, Takeshi Kishida, Hiroshi Kadota

IEEE J. Solid State Circuits, March, 1992

An Accurate, High Speed Implementation of Division by the Quasi-Unity Divisor Method.

Hiraku Nakano, Masaitsu Nakajima, Yasuhiro Nakakura, Tadahiro Yoshida, Yoshiyuki Goi, Yuji Nakai, Reiji Segawa, Takeshi Kishida

Proceedings of the Algorithms, Software, Architecture, 1992

1991

OHMEGA: A VLSI Superscalar Processor Architecture for Numerical Applications.

Masaitsu Nakajima, Hiraku Nakano, Yasuhiro Nakakura, Tadahiro Yoshida, Yoshiyuki Goi, Yuji Nakai, Reiji Segawa, Takeshi Kishida, Hiroshi Kadota

Proceedings of the 18th Annual International Symposium on Computer Architecture. Toronto, 1991

Parallel computer ADENART - its architecture and application.

Hiroshi Kadota, Katsuyuki Kaneko, Ichiro Okabayashi, Tadashi Okamoto, T. Mimura, Yasuhiro Nakakura, Akiyoshi Wakatani, Masaitsu Nakajima, Junji Nishikawa, K. Zaiki, Tatsuo Nogi

Proceedings of the 5th international conference on Supercomputing, 1991

1990

Processing element design for a parallel computer.

Katsuyuki Kaneko, Masaitsu Nakajima, Yasuhiro Kakakura, Junji Nishikawa, Ichiro Okabayashi, Hiroshi Kadota

IEEE Micro, 1990

1989

A VLSI RISC with 20-MFLOPS peak, 64-bit floating-point unit.

Katsuyuki Kaneko, Tadashi Okamoto, Masaitsu Nakajima, Yasuhiro Nakakura, Satoshi Gokita, Junji Nishikawa, Yuji Tanikawa, Hiroshi Kadota

IEEE J. Solid State Circuits, October, 1989