Masahito Matsuo

According to our database, Masahito Matsuo authored at least 5 papers between 1988 and 1997.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

1997

A dual-issue RISC processor for multimedia signal processing.

Hisakazu Sato, Edgar Holmann, Toyohiko Yoshida, Masahito Matsuo, Toru Kengaku

Proceedings of the 1997 IEEE International Conference on Acoustics, 1997

1994

A 32-bit Superscalar Microprocessor with 64-Bit Processing and High Bandwidth DRAM Interface.

Masahito Matsuo, Hiroyuki Kondo, Yukari Takata, Souichi Kobayashi, Mitsugu Satoh, Toyohiko Yoshida, Yuichi Saitoh, Jun-ichi Hinata

Proceedings of the Proceedings 1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1994

1990

A strategy for avoiding pipeline interlock delays in a microprocessor.

Toyohiko Yoshida, Masahito Matsuo, Tatsuya Ueda, Yuichi Saito

Proceedings of the 1990 IEEE International Conference on Computer Design: VLSI in Computers and Processors, 1990

1989

A 32-bit microprocessor with high performance bit-map manipulation instructions.

Toru Shimizu, Shunichi Iwata, Yuichi Saito, Toyohiko Yoshida, Masahito Matsuo, Junichi Hinata, Kazunori Saito

Proceedings of the Computer Design: VLSI in Computers and Processors, 1989

1988

A 32-bit Microprocessor Based on the TRON Architecture: Design of the GMICRO/100.

Tom Shimizu, Toyohiko Yoshida, Yuichi Saitoh, Masahito Matsuo, Tatsuya Enomoto

Proceedings of the COMPCON'88, Digest of Papers, Thirty-Third IEEE Computer Society International Conference, San Francisco, California, USA, February 29, 1988