Masahiro Sowa
According to our database1,
Masahiro Sowa
authored at least 41 papers
between 1982 and 2012.
Collaborative distances:
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Bibliography
2012
An FPGA-Based Information Detection Hardware System Employing Multi-Match Content Addressable Memory.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2012
2010
2009
Trans. High Perform. Embed. Archit. Compil., 2009
Parallel Comput., 2009
2008
J. Parallel Distributed Comput., 2008
Comput. Lang. Syst. Struct., 2008
Proceedings of the 9th International Symposium on Parallel Architectures, 2008
2007
J. Mobile Multimedia, 2007
J. Convergence Inf. Technol., 2007
Proceedings of the 19th Symposium on Computer Architecture and High Performance Computing (SBAC-PAD 2007), 2007
Proceedings of the Eighth International Conference on Parallel and Distributed Computing, 2007
Proceedings of the 2007 International Conference on Parallel Processing Workshops (ICPP Workshops 2007), 2007
An Efficient Code Generation Algorithm for Code Size Reduction Using 1-Offset P-Code Queue Computation Model.
Proceedings of the Embedded and Ubiquitous Computing, International Conference, 2007
2006
High-Level Modeling and FPGA Prototyping of Produced Order Parallel Queue Processor Core.
J. Supercomput., 2006
Inf. Media Technol., 2006
On the Design of a Dual-Execution Modes Processor: Architecture and Preliminary Evaluation.
Proceedings of the Frontiers of High Performance Computing and Networking, 2006
Proceedings of the 2006 International Conference on Parallel Processing Workshops (ICPP Workshops 2006), 2006
2005
J. Supercomput., 2005
Proceedings of the Embedded and Ubiquitous Computing, 2005
Modular Design Structure and High-Level Prototyping for Novel Embedded Processor Core.
Proceedings of the Embedded and Ubiquitous Computing, 2005
2003
Proceedings of the Parallel and Distributed Processing and Applications, 2003
2002
Proposal and Design of a Parallel Queue Processor Architecture (PQP).
Proceedings of the International Conference on Parallel and Distributed Computing Systems, 2002
Compiler-Controlled Parallelism-Independent Scheduling for Parallel and Distributed Systems.
Proceedings of the Applied Parallel Computing Advanced Scientific Computing, 2002
Compiler-Controlled Parallelism-Independent Scheduling Method for Cluster Computing Systems.
Proceedings of the 16th Annual International Symposium on High Performance Computing Systems and Applications, 2002
2001
Access route control by an extended key/lock scheme.
Comput. Syst. Sci. Eng., 2001
1997
Intruction Fetch Mechanism for PN-Superscalar.
Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 1997
Program Controlled Cache Memory on Parallel Computer.
Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 1997
1996
Hybrid Processor Based on VLIW and PN-Superscalar.
Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 1996
1994
V++: An Instruction-Restructurable Processor Architecture.
Proceedings of the 27th Annual Hawaii International Conference on System Sciences (HICSS-27), 1994
1993
A static processor-scheduling algorithm resistive to dynamic fluctuation of execution timing.
Syst. Comput. Jpn., 1993
1992
Syst. Comput. Jpn., 1992
Syst. Comput. Jpn., 1992
1991
Parallel execution on the function-partitioned processor with multiple instruction streams.
Syst. Comput. Jpn., 1991
Int. J. High Speed Comput., 1991
1987
A Method for Speeding up Serial Processing in Dataflow Computers by Means of a Program Counter.
Comput. J., 1987
1985
A Timed Petri Net Model and Simulation of a Dataflow Computer.
Proceedings of the International Workshop on Timed Petri Nets, 1985
1982
IEEE Trans. Computers, 1982