Masahiro Sakamoto

According to our database, Masahiro Sakamoto authored at least 14 papers between 1998 and 2024.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2024

Page Turning Using Assistive Robot with Low-Degree-of-Freedom Hand.

Hidetoshi Ikeda, Yuta Mizukami, Masahiro Sakamoto, Takumi Saeki, Hokyoo Lee, Masakazu Hori

Sensors, October, 2024

Development and Implementation Results of a DX Literacy Standard Skills Survey Using Generative AI.

Masahiro Sakamoto, Yukihiro Matsubara, Kousuke Mouri

Proceedings of the 16th IIAI International Congress on Advanced Applied Informatics, 2024

2023

Learning Analysis infrastructure to support optimal learning based on IRT and Video Enrollment Data.

Masahiro Sakamoto, Yukihiro Matsubara, Kousuke Mouri

Proceedings of the Proceeding of the 31st International Conference on Computers in Education, 2023

2015

A Sigma-Delta Domain Lowpass Wave Filter.

Hisato Fujisaka, Takeshi Kamio, Chang-Jun Ahn, Masahiro Sakamoto, Kazuhisa Haeiwa

IEEE Trans. Circuits Syst. I Regul. Pap., 2015

2014

Development of immersive display system of web service in living space.

Hiroshi Sugimura, Kazuki Utsumi, Masayuki Kaneko, Kazuki Arima, Masahiro Sakamoto, Yuki Imaizumi, Tomoki Watanabe, Masao Isshiki

Proceedings of the IEEE 3rd Global Conference on Consumer Electronics, 2014

2012

Sorter-Based Arithmetic Circuits for Sigma-Delta Domain Signal Processing - Part II: Multiplication and Algebraic Functions.

Hisato Fujisaka, Masahiro Sakamoto, Chang-Jun Ahn, Takeshi Kamio, Kazuhisa Haeiwa

IEEE Trans. Circuits Syst. I Regul. Pap., 2012

Sorter-Based Arithmetic Circuits for Sigma-Delta Domain Signal Processing - Part I: Addition, Approximate Transcendental Functions, and Log-Domain Operations.

Hisato Fujisaka, Takeshi Kamio, Chang-Jun Ahn, Masahiro Sakamoto, Kazuhisa Haeiwa

IEEE Trans. Circuits Syst. I Regul. Pap., 2012

2004

A design of 4-operand redundant binary parallel adder using neuron MOS.

Masahiro Sakamoto, Shuusaku Mizukami, Daisuke Hamano, Hisato Fujisaka

Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

A binary-quantized pseudo-diffusion system.

Hisato Fujisaka, Daisuke Hamano, Masahiro Sakamoto, Takeshi Kamio

Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

2002

Design of a multiple-operand redundant binary adder.

Masahiro Sakamoto, Daisuke Hamano, Mititada Morisue

Syst. Comput. Jpn., 2002

Bit-Stream Signal Processing Circuits and Their Application.

Hisato Fujisaka, Masahiro Sakamoto, Mititada Morisue

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2002

Piecewise linear operations on sigma-delta modulated signals.

Yuji Hidaka, Hisato Fujisaka, Masahiro Sakamoto, Mititada Morisue

Proceedings of the 2002 9th IEEE International Conference on Electronics, 2002

1999

Arithmetic circuits for single-bit digital signal processing.

Hisato Fujisaka, Naoyuki Masuda, Masahiro Sakamoto, Mititada Morisue

Proceedings of the 6th IEEE International Conference on Electronics, Circuits and Systems, 1999

1998

A Josephson Ternary Memory Circuit.

Mititada Morisue, Jun Endo, Toshimitu Morooka, Nobuhiro Shimizu, Masahiro Sakamoto

Proceedings of the 28th IEEE International Symposium on Multiple-Valued Logic, 1998