Masahiro Kaminaga

According to our database1, Masahiro Kaminaga authored at least 16 papers between 2008 and 2024.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

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Bibliography

2024
On SIS-problem-based random Feistel ciphers and its statistical evaluation of resistance against differential cryptanalysis.
IACR Cryptol. ePrint Arch., 2024

2023
Upper Bound for the Coefficients of the Shortest Vector of Random Lattice.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., December, 2023

2022
Improving genetic algorithms for solving the SVP: focusing on low memory consumption and high reproducibility.
Iran J. Comput. Sci., 2022

Random Numbers Generated by the Oscillator Sampling Method as a Renewal Process.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2022

2020
A True Random Number Generator Method Embedded in Wireless Communication Systems.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2020

2019
Determining the Optimal Random-Padding Size for Rabin Cryptosystems.
IEEE Trans. Inf. Forensics Secur., 2019

2018
Crashing Modulus Attack on Modular Squaring for Rabin Cryptosystem.
IEEE Trans. Dependable Secur. Comput., 2018

2015
Double Counting in 2<sup>t</sup>-ary RSA Precomputation Reveals the Secret Exponent.
IEEE Trans. Inf. Forensics Secur., 2015

2014
Round Addition DFA on SPN Block Ciphers.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2014

Double Counting in $2^t$-ary RSA Precomputation Reveals the Secret Exponent.
CoRR, 2014

Secret key reconstruction method using round addition DFA on lightweight block cipher LBlock.
Proceedings of the International Symposium on Information Theory and its Applications, 2014

2013
Round Addition DFA on 80-bit Piccolo and TWINE.
IEICE Trans. Inf. Syst., 2013

Round Addition Using Faults for Generalized Feistel Network.
IEICE Trans. Inf. Syst., 2013

Round addition DFA for microcontroller implemented the triple DES.
Proceedings of the IEEE 2nd Global Conference on Consumer Electronics, 2013

2011
Development and evaluation of a microstep DFA vulnerability estimation method.
IEICE Electron. Express, 2011

2008
Logic-Level Analysis of Fault Attacks and a Cost-Effective Countermeasure Design.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008


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