Masahiro Iida

According to our database, Masahiro Iida authored at least 88 papers between 2002 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2024

Applying Run-Length Compression to the Configuration Data of SLM Fine-Grained Reconfigurable Logic.

Souhei Takagi, Takuya Kojima, Hideharu Amano, Morihiro Kuga, Masahiro Iida

IEICE Trans. Inf. Syst., 2024

SLMLET: A RISC-V Processor SoC with Tightly-Coupled Area-Efficient eFPGA Blocks.

Takuya Kojima, Yosuke Yanai, Hayate Okuhara, Hideharu Amano, Morihiro Kuga, Masahiro Iida

Proceedings of the IEEE Symposium in Low-Power and High-Speed Chips, 2024

2023

An eFPGA Generation Suite with Customizable Architecture and IDE.

Morihiro Kuga, Qian Zhao, Yuya Nakazato, Motoki Amagasaki, Masahiro Iida

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., March, 2023

2022

A Posit Based Multiply-accumulate Unit with Small Quire Size for Deep Neural Networks.

Yasuhiro Nakahara, Yuta Masuda, Masato Kiyama, Motoki Amagasaki, Masahiro Iida

IPSJ Trans. Syst. LSI Des. Methodol., 2022

Reconfigurable Neural Network Accelerator and Simulator for Model Implementation.

Yasuhiro Nakahara, Masato Kiyama, Motoki Amagasaki, Qian Zhao, Masahiro Iida

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2022

Towards the Design of Locally Differential Private Hardware System for Edge Computing.

Kaito Taguchi, Kouichi Sakurai, Masahiro Iida

Proceedings of the Tenth International Symposium on Computing and Networking, 2022

FPL Demo: An FPGA-IP Prototype Chip for MEC devices.

Morihiro Kuga, Masahiro Iida, Hideharu Amano

Proceedings of the 32nd International Conference on Field-Programmable Logic and Applications, 2022

2021

Development of Quantized DNN Library for Exact Hardware Emulation.

Masato Kiyama, Motoki Amagasaki, Masahiro Iida

CoRR, 2021

Automatic executable code generation for DNN accelerator ReNA.

Yuta Masuda, Yasuhiro Nakahara, Motoki Amagasaki, Masahiro Iida

Proceedings of the Ninth International Symposium on Computing and Networking, 2021

Automation of Domain-specific FPGA-IP Generation and Test.

Yuya Nakazato, Motoki Amagasaki, Qian Zhao, Masahiro Iida, Morihiro Kuga

Proceedings of the HEART '21: 11th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies, 2021

2020

R-GCN Based Function Inference for Gate-level Netlist.

Motoki Amagasaki, Hiroki Oyama, Yuichiro Fujishiro, Masahiro Iida, Hiroaki Yasuda, Hiroto Ito

IPSJ Trans. Syst. LSI Des. Methodol., 2020

Relationship between Recognition Accuracy and Numerical Precision in Convolutional Neural Network Models.

Yasuhiro Nakahara, Masato Kiyama, Motoki Amagasaki, Masahiro Iida

IEICE Trans. Inf. Syst., 2020

Image Search System Based on Feature Vectors of Convolutional Neural Network.

Mery Diana, Motoki Amagasaki, Masahiro Iida

Proceedings of the 2020 IEEE Region 10 Conference, 2020

A Microcode-based Control Unit for Deep Learning Processors.

Qian Zhao, Yasuhiro Nakahara, Motoki Amagasaki, Masahiro Iida, Takaichi Yoshida

Proceedings of the 2020 IEEE International Parallel and Distributed Processing Symposium Workshops, 2020

Architecture-aware Cost Function for 3D FPGA Placement Using Convolutional Neural Network.

Qian Zhao, Motoki Amagasaki, Masahiro Iida, Takaichi Yoshida

Proceedings of the Eighth International Symposium on Computing and Networking, 2020

2019

A SLM-based overlay architecture for fine-grained virtual FPGA.

Theingi Myint, Motoki Amagasaki, Qian Zhao, Masahiro Iida

IEICE Electron. Express, 2019

A Novel SLM-Based Virtual FPGA Overlay Architecture.

Theingi Myint, Motoki Amagasaki, Qian Zhao, Masahiro Iida, Masato Kiyama

Proceedings of the 13th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2019

Deep Learning Framework with Arbitrary Numerical Precision.

Masato Kiyama, Motoki Amagasaki, Masahiro Iida

Proceedings of the 13th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2019

A Quantized Neural Network Library for Proper Implementation of Hardware Emulation.

Masato Kiyama, Yasuhiro Nakahara, Motoki Amagasaki, Masahiro Iida

Proceedings of the Seventh International Symposium on Computing and Networking Workshops, 2019

A Resource Reduced Application-Specific FPGA Switch.

Qian Zhao, Yoshimasa Ohnishi, Masahiro Iida, Takaichi Yoshida

Proceedings of the Applied Reconfigurable Computing - 15th International Symposium, 2019

2018

Enabling FPGA-as-a-Service in the Cloud with hCODE Platform.

Qian Zhao, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi

IEICE Trans. Inf. Syst., 2018

Order Adjustment Approach Using Cayley Graphs for the Order/Degree Problem.

Teruaki Kitasuka, Takayuki Matsuzaki, Masahiro Iida

IEICE Trans. Inf. Syst., 2018

Three Dimensional FPGA Architecture with Fewer TSVs.

Motoki Amagasaki, Masato Ikebe, Qian Zhao, Masahiro Iida, Toshinori Sueyoshi

IEICE Trans. Inf. Syst., 2018

Design Methodology.

Masahiro Iida

Proceedings of the Principles and Structures of FPGAs., 2018

What Is an FPGA?

Masahiro Iida

Proceedings of the Principles and Structures of FPGAs., 2018

2017

Towards Open-HW: A Platform to Design, Share and Deploy FPGA Accelerators in Low Cost.

Qian Zhao, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi

IPSJ Trans. Syst. LSI Des. Methodol., 2017

Physical Fault Detection and Recovery Methods for System-LSI Loaded FPGA-IP Core.

Motoki Amagasaki, Yuki Nishitani, Kazuki Inoue, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi

IEICE Trans. Inf. Syst., 2017

High-level Synthesis based on Parallel Design Patterns using a Functional Language.

Morihiro Kuga, Kansuke Fukuda, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi

Proceedings of the 8th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies, 2017

FPGA based ASIC Emulator with High Speed Optical Serial Links.

Motoki Amagasaki, Futoshi Murase, Morihiro Kuga, Masahiro Iida, Toshinori Sueyoshi

Proceedings of the 8th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies, 2017

hCODE 2.0: An open-source toolkit for building efficient FPGA-enabled clouds.

Qian Zhao, Hendarmawan, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi

Proceedings of the International Conference on Field Programmable Technology, 2017

A Study of FPGA Virtualization and Accelerator Scheduling.

Qian Zhao, Masahiro Iida, Toshinori Sueyoshi

Proceedings of the first Workshop on Emerging Technologies for software-defined and reconfigurable hardware-accelerated Cloud Datacenters, 2017

2016

A Study of Heterogeneous Computing Design Method based on Virtualization Technology.

Qian Zhao, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi

SIGARCH Comput. Archit. News, 2016

SLM: A Scalable Logic Module Architecture with Less Configuration Memory.

Motoki Amagasaki, Ryo Araki, Masahiro Iida, Toshinori Sueyoshi

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2016

A Heuristic Method of Generating Diameter 3 Graphs for Order/Degree Problem.

Teruaki Kitasuka, Masahiro Iida

CoRR, 2016

A novel soft error tolerant FPGA architecture.

Motoki Amagasaki, Yuji Nakamura, Takuya Teraoka, Masahiro Iida, Toshinori Sueyoshi

Proceedings of the 2016 IFIP/IEEE International Conference on Very Large Scale Integration, 2016

A heuristic method of generating diameter 3 graphs for order/degree problem (invited paper).

Teruaki Kitasuka, Masahiro Iida

Proceedings of the Tenth IEEE/ACM International Symposium on Networks-on-Chip, 2016

An area compact soft error resident circuit for FPGA.

Motoki Amagasaki, Yuji Nakamura, Takuya Teraoka, Masahiro Iida, Toshinori Sueyoshi

Proceedings of the International Conference on IC Design and Technology, 2016

hCODE: An open-source platform for FPGA accelerators.

Qian Zhao, Takuya Nakamichi, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi

Proceedings of the 2016 International Conference on Field-Programmable Technology, 2016

2015

A 3D FPGA Architecture to Realize Simple Die Stacking.

Motoki Amagasaki, Qian Zhao, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi

IPSJ Trans. Syst. LSI Des. Methodol., 2015

Fault-Tolerant FPGA: Architectures and Design for Programmable Logic Intellectual Property Core in SoC.

Motoki Amagasaki, Qian Zhao, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi

IEICE Trans. Inf. Syst., 2015

Architecture exploration of 3D FPGA to minimize internal layer connection.

Motoki Amagasaki, Yuto Takeuchi, Qian Zhao, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi

Proceedings of the 2015 IFIP/IEEE International Conference on Very Large Scale Integration, 2015

Simple wafer stacking 3D-FPGA architecture.

Motoki Amagasaki, Qian Zhao, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi

Proceedings of the 2015 International Conference on IC Design & Technology, 2015

2014

Blokus Duo engine on a Zynq.

Susumu Mashimo, Kansuke Fukuda, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi

Proceedings of the 2014 International Conference on Field-Programmable Technology, 2014

Zyndroid: An Android platform for software/hardware coprocessing.

Susumu Mashimo, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi

Proceedings of the 2014 International Conference on Field-Programmable Technology, 2014

A novel three-dimensional FPGA architecture with high-speed serial communication links.

Takuya Kajiwara, Qian Zhao, Motoki Amagasaki, Masahiro Iida, Morituro Kuga, Toshinori Sueyoshi

Proceedings of the 2014 International Conference on Field-Programmable Technology, 2014

A logic cell architecture exploiting the shannon expansion for the reduction of configuration memory.

Qian Zhao, Kyosei Yanagida, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi

Proceedings of the 24th International Conference on Field Programmable Logic and Applications, 2014

2013

A reconfigurable Java accelerator with software compatibility for embedded systems.

Yuki Ogawa, Masahiro Iida, Motoki Amagasaki, Morihiro Kuga, Toshinori Sueyoshi

SIGARCH Comput. Archit. News, 2013

FPGA Design Framework Combined with Commercial VLSI CAD.

Qian Zhao, Kazuki Inoue, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi

IEICE Trans. Inf. Syst., 2013

Three-dimensional stacking FPGA architecture using face-to-face integration.

Tetsuro Hamada, Qian Zhao, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi

Proceedings of the 21st IEEE/IFIP International Conference on VLSI and System-on-Chip, 2013

An FPGA design and implementation framework combined with commercial VLSI CADs.

Qian Zhao, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi

Proceedings of the 2013 8th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC), 2013

An automatic FPGA design and implementation framework.

Qian Zhao, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi

Proceedings of the 23rd International Conference on Field programmable Logic and Applications, 2013

Defect-robust FPGA architectures for intellectual property cores in system LSI.

Motoki Amagasaki, Kazuki Inoue, Qian Zhao, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi

Proceedings of the 23rd International Conference on Field programmable Logic and Applications, 2013

A novel FPGA design framework with VLSI post-routing performance analysis (abstract only).

Qian Zhao, Kazuki Inoue, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi

Proceedings of the 2013 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2013

2012

An Easily Testable Routing Architecture and Prototype Chip.

Kazuki Inoue, Masahiro Koga, Motoki Amagasaki, Masahiro Iida, Yoshinobu Ichida, Mitsuro Saji, Jun Iida, Toshinori Sueyoshi

IEICE Trans. Inf. Syst., 2012

COGRE: A Novel Compact Logic Cell Architecture for Area Minimization.

Masahiro Iida, Motoki Amagasaki, Yasuhiro Okamoto, Qian Zhao, Toshinori Sueyoshi

IEICE Trans. Inf. Syst., 2012

Fault-Injection Analysis to Estimate SEU Failure in Time by Using Frame-Based Partial Reconfiguration.

Yoshihiro Ichinomiya, Tsuyoshi Kimura, Motoki Amagasaki, Morihiro Kuga, Masahiro Iida, Toshinori Sueyoshi

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2012

Evaluation of fault tolerant technique based on homogeneous FPGA architecture.

Yuki Nishitani, Kazuki Inoue, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi

Proceedings of the 20th IEEE/IFIP International Conference on VLSI and System-on-Chip, 2012

A novel physical defects recovery technique for FPGA-IP cores.

Yuki Nishitani, Kazuki Inoue, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi

Proceedings of the 2012 International Conference on Reconfigurable Computing and FPGAs, 2012

A Bitstream Relocation Technique to Improve Flexibility of Partial Reconfiguration.

Yoshihiro Ichinomiya, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi

Proceedings of the Algorithms and Architectures for Parallel Processing, 2012

Fault Recovery Technique for TMR Softcore Processor System Using Partial Reconfiguration.

Makoto Fujino, Hiroki Tanaka, Yoshihiro Ichinomiya, Motoki Amagasaki, Morihiro Kuga, Masahiro Iida, Toshinori Sueyoshi

Proceedings of the Algorithms and Architectures for Parallel Processing, 2012

Accelerated evaluation of SEU failure-in-time using frame-based partial reconfiguration.

Yoshihiro Ichinomiya, Kohei Takano, Motoki Amagasaki, Morihiro Kuga, Masahiro Iida, Toshinori Sueyoshi

Proceedings of the 2012 International Conference on Field-Programmable Technology, 2012

Fault detection and avoidance of FPGA in various granularities.

Kazuki Inoue, Yuki Nishitani, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi

Proceedings of the 22nd International Conference on Field Programmable Logic and Applications (FPL), 2012

Designing Flexible Reconfigurable Regions to Relocate Partial Bitstreams.

Yoshihiro Ichinomiya, Sadaki Usagawa, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi

Proceedings of the 2012 IEEE 20th Annual International Symposium on Field-Programmable Custom Computing Machines, 2012

2011

Parallelization of the channel width search for FPGA routing.

Hiroomi Sawada, Morihiro Kuga, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi

SIGARCH Comput. Archit. News, 2011

Improving the Soft-error Tolerability of a Soft-core Processor on.

Yoshihiro Ichinomiya, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi

J. Next Gener. Inf. Technol., 2011

A Genuine Power-Gatable Reconfigurable Logic Chip with FeRAM Cells.

Masahiro Iida, Masahiro Koga, Kazuki Inoue, Motoki Amagasaki, Yoshinobu Ichida, Mitsuro Saji, Jun Iida, Toshinori Sueyoshi

IEICE Trans. Electron., 2011

A Novel Soft Error Detection and Correction Circuit for Embedded Reconfigurable Systems.

Qian Zhao, Yoshihiro Ichinomiya, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi

IEEE Embed. Syst. Lett., 2011

An easily testable routing architecture of FPGA.

Masahiro Iida, Kazuki Inoue, Motoki Amagasaki, Toshinori Sueyoshi

Proceedings of the IEEE/IFIP 19th International Conference on VLSI and System-on-Chip, 2011

An Easily Testable Routing Architecture and Efficient Test Technique.

Kazuki Inoue, Hiroki Yosho, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi

Proceedings of the International Conference on Field Programmable Logic and Applications, 2011

A novel reconfigurable logic device base on 3D stack technology.

Qian Zhao, Yusuke Iwai, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi

Proceedings of the 2011 IEEE International 3D Systems Integration Conference (3DIC), Osaka, Japan, January 31, 2011

2010

A Variable-Grain Logic Cell and Routing Architecture for a Reconfigurable IP Core.

Kazuki Inoue, Qian Zhao, Yasuhiro Okamoto, Hiroki Yosho, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi

ACM Trans. Reconfigurable Technol. Syst., 2010

Power-aware FPGA routing fabrics and design tools.

Shoichi Nishida, Jyunya Eto, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi

Proceedings of the 18th IEEE/IFIP VLSI-SoC 2010, 2010

A robust reconfigurable logic device based on less configuration memory logic cell.

Qian Zhao, Yoshihiro Ichinomiya, Yasuhiro Okamoto, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi

Proceedings of the International Conference on Field-Programmable Technology, 2010

COGRE: A Configuration Memory Reduced Reconfigurable Logic Cell Architecture for Area Minimization.

Yasuhiro Okamoto, Yoshihiro Ichinomiya, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi

Proceedings of the International Conference on Field Programmable Logic and Applications, 2010

First Prototype of a Genuine Power-Gatable Reconfigurable Logic Chip with FeRAM Cells.

Masahiro Koga, Masahiro Iida, Motoki Amagasaki, Yoshinobu Ichida, Mitsuro Saji, Jun Iida, Toshinori Sueyoshi

Proceedings of the International Conference on Field Programmable Logic and Applications, 2010

Improving the Robustness of a Softcore Processor against SEUs by Using TMR and Partial Reconfiguration.

Yoshihiro Ichinomiya, Shiro Tanoue, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi

Proceedings of the 18th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2010

2009

Improvement of Execution Efficiency on the MX Core.

Mitsutaka Nakano, Masahiro Iida, Toshinori Sueyoshi

Proceedings of the 2009 International Conference on Parallel and Distributed Computing, 2009

A Novel Local Interconnect Architecture for Variable Grain Logic Cell.

Kazuki Inoue, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi

Proceedings of the Reconfigurable Computing: Architectures, 2009

2008

An Embedded Reconfigurable IP Core with Variable Grain Logic Cell Architecture.

Motoki Amagasaki, Ryoichi Yamaguchi, Masahiro Koga, Masahiro Iida, Toshinori Sueyoshi

Int. J. Reconfigurable Comput., 2008

2007

A Novel Technique to Design Energy-Efficient Contexts for Reconfigurable Logic Devices.

Hiroshi Shinohara, Hideaki Monji, Masahiro Iida, Toshinori Sueyoshi

IEICE Trans. Inf. Syst., 2007

An Embedded Reconfigurable Logic Core based on Variable Grain Logic Cell Architecture.

Yoshiaki Satou, Motoki Amagasaki, Hiroshi Miura, Kazunori Matsuyama, Ryoichi Yamaguchi, Masahiro Iida, Toshinori Sueyoshi

Proceedings of the 2007 International Conference on Field-Programmable Technology, 2007

A Variable Grain Logic Cell Architecture for Reconfigurable Logic Cores.

Motoki Amagasaki, Ryoichi Yamaguchi, Kazunori Matsuyama, Masahiro Iida, Toshinori Sueyoshi

Proceedings of the FPL 2007, 2007

A Novel Technique to Create Energy-Efficient Contexts for Reconfigurable Logic.

Hiroshi Shinohara, Hideaki Monji, Masahiro Iida, Toshinori Sueyoshi

Proceedings of the IEEE Symposium on Field-Programmable Custom Computing Machines, 2007

Evaluating Variable-Grain Logic Cells Using Heterogeneous Technology Mapping.

Kazunori Matsuyama, Motoki Amagasaki, Hideaki Nakayama, Ryoichi Yamaguchi, Masahiro Iida, Toshinori Sueyoshi

Proceedings of the Reconfigurable Computing: Architectures, 2007

2006

Evaluation of Variable Grain Logic Cell Architecture for Reconfigurable Device.

Motoki Amagasaki, Takurou Shimokawa, Kazunori Matsuyama, Ryoichi Yamaguchi, Hideaki Nakayama, Naoto Hamabe, Masahiro Iida, Toshinori Sueyoshi

Proceedings of the IFIP VLSI-SoC 2006, 2006

Effective clustering technique to optimize routability of outer cluster nets.

Masaki Kobata, Masahiro Iida, Toshinori Sueyoshi

Proceedings of the ACM/SIGDA 14th International Symposium on Field Programmable Gate Arrays, 2006

2005

Applying the Small-World Network to Routing Structure of FPGAs.

Hisashi Tsukiashi, Masahiro Iida, Toshinori Sueyoshi

Proceedings of the 2005 International Conference on Field Programmable Logic and Applications (FPL), 2005

2002

Configurable and Reconfigurable Computing for Digital Signal Processing.

Toshinori Sueyoshi, Masahiro Iida

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2002