Masahiro Hatanaka

According to our database1, Masahiro Hatanaka authored at least 3 papers between 1989 and 1994.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

1989
1990
1991
1992
1993
1994
0
1
2
1
1
1

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

1994
Memory array architecture and decoding scheme for 3 V only sector erasable DINOR flash memory.
IEEE J. Solid State Circuits, April, 1994

1990
A 24-b 50-ns digital image signal processor.
IEEE J. Solid State Circuits, December, 1990

1989
A 400 K-transistor CMOS sea-of-gates array with continuous track allocation.
IEEE J. Solid State Circuits, October, 1989


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