Masahiro Fujita

Yasuoki Iida

Proceedings of the Innovative Mobile and Internet Services in Ubiquitous Computing, 2021

Logic Synthesis Meets Machine Learning: Trading Exactness for Generalization.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

Logic Synthesis for Generalization and Learning Addition.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

A Decomposition-Based Synthesis Algorithm for Sparse Matrix-Vector Multiplication in Parallel Communication Structure.

[BibT_eX]

[DOI]

Mingfei Yu

Ruitao Gao

Proceedings of the ASPDAC '21: 26th Asia and South Pacific Design Automation Conference, 2021

2020

A Methodology to Capture Fine-Grained Internal Visibility During Multisession Silicon Debug.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2020

A Calibration Technique for Simultaneous Estimation of Actual Sensing Matrix Coefficients on Modulated Wideband Converters.

[BibT_eX]

[DOI]

Zolboo Byambadorj

Koji Asami

Takahiro J. Yamaguchi

Akio Higo

Tetsuya Iizuka

IEEE Trans. Circuits Syst., 2020

Theoretical Analysis of Noise Figure for Modulated Wideband Converter.

[BibT_eX]

[DOI]

Zolboo Byambadorj

Koji Asami

Takahiro J. Yamaguchi

Akio Higo

Tetsuya Iizuka

IEEE Trans. Circuits Syst. I Regul. Pap., 2020

An Automatic Test Pattern Generation Method for Multiple Stuck-At Faults by Incrementally Extending the Test Patterns.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

Post-Silicon Gate-Level Error Localization With Effective and Combined Trace Signal Selection.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

A Logic Optimization Method by Eliminating Redundant Multiple Faults from Higher to Lower Cardinality.

[BibT_eX]

[DOI]

IPSJ Trans. Syst. LSI Des. Methodol., 2020

Synthesis and Generalization of Parallel Algorithm for Matrix-vector Multiplication.

[BibT_eX]

[DOI]

IPSJ Trans. Syst. LSI Des. Methodol., 2020

HIVE: A cross-platform, modular visualization framework for large-scale data sets.

[BibT_eX]

[DOI]

Future Gener. Comput. Syst., 2020

Parallel Scheduling Self-attention Mechanism: Generalization and Optimization.

[BibT_eX]

[DOI]

Mingfei Yu

CoRR, 2020

Development and field test of the articulated mobile robot T2 Snake-4 for plant disaster prevention.

[BibT_eX]

[DOI]

Adv. Robotics, 2020

Development of a folding arm on an articulated mobile robot for plant disaster prevention.

[BibT_eX]

[DOI]

Adv. Robotics, 2020

What are the important technologies for bin picking? Technology analysis of robots in competitions based on a set of performance metrics.

[BibT_eX]

[DOI]

Gustavo Alfonso Garcia Ricardez

Yukiyasu Domae

Akio Noda

Adv. Robotics, 2020

A Low Overhead Methodology for Validating Memory Consistency Models in Chip Multiprocessors.

[BibT_eX]

[DOI]

Proceedings of the 33rd International Conference on VLSI Design and 19th International Conference on Embedded Systems, 2020

SAT-Based Mapping of Data-Flow Graphs onto Coarse-Grained Reconfigurable Arrays.

[BibT_eX]

[DOI]

Proceedings of the VLSI-SoC: Design Trends, 2020

SAT-Based Data-Flow Mapping Onto Array Processor.

[BibT_eX]

[DOI]

Proceedings of the 28th IFIP/IEEE International Conference on Very Large Scale Integration, 2020

Synthesis and Generalization of Parallel Algorithms Considering Communication Constraints.

[BibT_eX]

[DOI]

Akihiro Goda

Proceedings of the 21st International Symposium on Quality Electronic Design, 2020

Real-Time Threshold-based Landslide Prediction System for Hilly Region using Wireless Sensor Networks.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference on Consumer Electronics - Taiwan, 2020

Synthesis and Optimization of Multiple Portions of Circuits for ECO based on Set-Covering and QBF Formulations.

[BibT_eX]

[DOI]

Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

LUT-based Circuit Approximation with Targeted Error Guarantees.

[BibT_eX]

[DOI]

Proceedings of the 29th IEEE Asian Test Symposium, 2020

Theoretical Analysis on Noise Performance of Modulated Wideband Converters for Analog Testing.

[BibT_eX]

[DOI]

Zolboo Byambadorj

Koji Asami

Takahiro J. Yamaguchi

Akio Higo

Tetsuya Iizuka

Proceedings of the 29th IEEE Asian Test Symposium, 2020

Micro Biometric Authentication Using Fingernail Surfaces: A Study of Practical Use.

[BibT_eX]

[DOI]

Proceedings of the Advanced Information Networking and Applications, 2020

2019

Development of Tough Snake Robot Systems.

[BibT_eX]

[DOI]

Proceedings of the Disaster Robotics - Results from the ImPACT Tough Robotics Challenge, 2019

Task-Space Control of Articulated Mobile Robots With a Soft Gripper for Operations.

[BibT_eX]

[DOI]

IEEE Trans. Robotics, 2019

Approximate DCT Design for Video Encoding Based on Novel Truncation Scheme.

[BibT_eX]

[DOI]

Heming Sun

Zhengxue Cheng

Shinji Kimura

IEEE Trans. Circuits Syst. I Regul. Pap., 2019

Data-path aware high-level ECO synthesis.

[BibT_eX]

[DOI]

Masoud Shiroei

Integr., 2019

Signal Selection Methods for Debugging Gate-Level Sequential Circuits.

[BibT_eX]

[DOI]

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2019

SAT-based Silicon Debug of Electrical Errors under Restricted Observability Enhancement.

[BibT_eX]

[DOI]

Binod Kumar

J. Electron. Test., 2019

An Incremental Automatic Test Pattern Generation Method for Multiple Stuck-at Faults.

[BibT_eX]

[DOI]

Proceedings of the 37th IEEE VLSI Test Symposium, 2019

A Methodology for SAT-Based Electrical Error Debugging During Post-Silicon Validation.

[BibT_eX]

[DOI]

Binod Kumar

Proceedings of the 32nd International Conference on VLSI Design and 18th International Conference on Embedded Systems, 2019

A 48 MHz 880-nW Standby Power Normally-Off MCU with 1 Clock Full Backup and 4.69-μs Wakeup Featuring 60-nm Crystalline In-Ga-Zn Oxide BEOL-FETs.

[BibT_eX]

[DOI]

Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019

Approximate Arithmetic Circuit Design Using a Fast and Scalable Method.

[BibT_eX]

[DOI]

Qi Lu

Proceedings of the 27th IFIP/IEEE International Conference on Very Large Scale Integration, 2019

Adder-Only Convolutional Neural Network with Binary Input Image.

[BibT_eX]

[DOI]

Proceedings of the 62nd IEEE International Midwest Symposium on Circuits and Systems, 2019

AI x Robotics: Technology Challenges and Opportunities in Sensors, Actuators, and Integrated Circuits.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Solid- State Circuits Conference, 2019

Automatic Test Pattern Generation for Double Stuck-at Faults Based on Test Patterns of Single Faults.

[BibT_eX]

[DOI]

Proceedings of the 20th International Symposium on Quality Electronic Design, 2019

Synthesis of Algorithm Considering Communication Structure of Distributed/Parallel Computing.

[BibT_eX]

[DOI]

Ashish Mittal

Proceedings of the 20th International Symposium on Quality Electronic Design, 2019

Basic and Advanced Researches in Logic Synthesis and their Industrial Contributions.

[BibT_eX]

[DOI]

Proceedings of the 2019 International Symposium on Physical Design, 2019

High-Level Engineering Change Through Programmable Datapath and SMT Solvers.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

Live Demonstration: Automatic Synthesis of Algorithms on Multi Chip/FPGA with Communication Constraints.

[BibT_eX]

[DOI]

Tomohiro Maruoka

Akihiro Goda

Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

Signal Selection Methods for Efficient Multi-Target Correction.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

Securing Scan through Plain-text Restriction.

[BibT_eX]

[DOI]

Proceedings of the 25th IEEE International Symposium on On-Line Testing and Robust System Design, 2019

Preventing Scan Attack through Test Response Encryption.

[BibT_eX]

[DOI]

Proceedings of the 2019 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2019

Bin-picking Robot using a Multi-gripper Switching Strategy based on Object Sparseness.

[BibT_eX]

[DOI]

Gustavo Alfonso Garcia Ricardez

Yukiyasu Domae

Ryosuke Kawanishi

Proceedings of the 15th IEEE International Conference on Automation Science and Engineering, 2019

Validating Multi-Processor Cache Coherence Mechanisms under Diminished Observability.

[BibT_eX]

[DOI]

Proceedings of the 28th IEEE Asian Test Symposium, 2019

Basic Study on Targeted E-mail Attack Method Using OSINT.

[BibT_eX]

[DOI]

Proceedings of the Advanced Information Networking and Applications, 2019

2018

An ATPG Method for Double Stuck-At Faults by Analyzing Propagation Paths of Single Faults.

[BibT_eX]

[DOI]

Conrad J. Moore

IEEE Trans. Circuits Syst. I Regul. Pap., 2018

Planar Omnidirectional Crawler Mobile Mechanism - Development of Actual Mechanical Prototype and Basic Experiments.

[BibT_eX]

[DOI]

IEEE Robotics Autom. Lett., 2018

Development and Testing of Force-Sensing Forceps Using FBG for Bilateral Micro-Operation System.

[BibT_eX]

[DOI]

IEEE Robotics Autom. Lett., 2018

C Description Reconstruction Method from a Revised Netlist for ECO Support.

[BibT_eX]

[DOI]

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2018

234Compositor: A flexible parallel image compositing framework for massively parallel visualization environments.

[BibT_eX]

[DOI]

Jorji Nonaka

Kenji Ono

Future Gener. Comput. Syst., 2018

Multiple Stuck-at Fault Testability Analysis of ROBDD Based Combinational Circuit Design.

[BibT_eX]

[DOI]

Toral Shah

Anzhela Yu. Matrosova

J. Electron. Test., 2018

Jamming layered membrane gripper mechanism for grasping differently shaped-objects without excessive pushing force for search and rescue missions.

[BibT_eX]

[DOI]

Adv. Robotics, 2018

Development of universal vacuum gripper for wall-climbing robot.

[BibT_eX]

[DOI]

Adv. Robotics, 2018

ELURA: A Methodology for Post-Silicon Gate-Level Error Localization Using Regression Analysis.

[BibT_eX]

[DOI]

Proceedings of the 31st International Conference on VLSI Design and 17th International Conference on Embedded Systems, 2018

Memory-system requirements for convolutional neural networks.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Memory Systems, 2018

A Large Data Visualization Framework for SPARC64 fx HPC Systems - Case Study: K Computer Operational Environment -.

[BibT_eX]

[DOI]

Proceedings of the 8th IEEE Symposium on Large Data Analysis and Visualization, 2018

Silicon Debug with Maximally Expanded Internal Observability Using Nearest Neighbor Algorithm.

[BibT_eX]

[DOI]

Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI, 2018

A 20ns-write 45ns-read and 1014-cycle endurance memory module composed of 60nm crystalline oxide semiconductor transistors.

[BibT_eX]

[DOI]

Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018

On Securing Scan Design Through Test Vector Encryption.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

A New Reconfigurable Architecture with Applications to IoT and Mobile Computing.

[BibT_eX]

[DOI]

Tomohiro Maruoka

Proceedings of the Internet of Things. Information Processing in an Increasingly Connected World, 2018

Micro Disposable Biometric Authentication: An Application Using Fingernail Minute Textures for Nonsensitive Services.

[BibT_eX]

[DOI]

Proceedings of the 2018 3rd International Conference on Biomedical Imaging, 2018

A Study on Open Source Software for Large-Scale Data Visualization on SPARC64fx based HPC Systems.

[BibT_eX]

[DOI]

Proceedings of the International Conference on High Performance Computing in Asia-Pacific Region, 2018

2017

Subthreshold Operation of CAAC-IGZO FPGA by Overdriving of Programmable Routing Switch and Programmable Power Switch.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2017

Embedded Memory and ARM Cortex-M0 Core Using 60-nm C-Axis Aligned Crystalline Indium-Gallium-Zinc Oxide FET Integrated With 65-nm Si CMOS.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2017

A Methodology for Trace Signal Selection to Improve Error Detection in Post-Silicon Validation.

[BibT_eX]

[DOI]

Proceedings of the 30th International Conference on VLSI Design and 16th International Conference on Embedded Systems, 2017

On Testing of Superscalar Processors in Functional Mode for Delay Faults.

[BibT_eX]

[DOI]

Proceedings of the 30th International Conference on VLSI Design and 16th International Conference on Embedded Systems, 2017

A new approach for constructing logic functions after ECO.

[BibT_eX]

[DOI]

Proceedings of the 2017 IFIP/IEEE International Conference on Very Large Scale Integration, 2017

Template based synthesis for high performance computing.

[BibT_eX]

[DOI]

Proceedings of the 2017 IFIP/IEEE International Conference on Very Large Scale Integration, 2017

Improving post-silicon error detection with topological selection of trace signals.

[BibT_eX]

[DOI]

Proceedings of the 2017 IFIP/IEEE International Conference on Very Large Scale Integration, 2017

A Formal Perspective on Effective Post-silicon Debug and Trace Signal Selection.

[BibT_eX]

[DOI]

Proceedings of the VLSI Design and Test - 21st International Symposium, 2017

Slyware Prevention: Threat of Websites Inducing Accidental Taps and Countermeasures.

[BibT_eX]

[DOI]

Proceedings of the Advances in Network-Based Information Systems, 2017

Testing multiple stuck-at faults of ROBDD based combinational circuit design.

[BibT_eX]

[DOI]

Toral Shah

Anzhela Yu. Matrosova

Binod Kumar

Proceedings of the 18th IEEE Latin American Test Symposium, 2017

Post-silicon observability enhancement with topology based trace signal selection.

[BibT_eX]

[DOI]

Proceedings of the 18th IEEE Latin American Test Symposium, 2017

Methods of equivalence checking and ECO support under C-based design through reproduction of C descriptions from implementation designs.

[BibT_eX]

[DOI]

Proceedings of the 18th International Symposium on Quality Electronic Design, 2017

Systematic approximate logic optimization using don't care conditions.

[BibT_eX]

[DOI]

Proceedings of the 18th International Symposium on Quality Electronic Design, 2017

A new approach for selecting inputs of logic functions during debug.

[BibT_eX]

[DOI]

Proceedings of the 18th International Symposium on Quality Electronic Design, 2017

A low-cost approximate 32-point transform architecture.

[BibT_eX]

[DOI]

Heming Sun

Zhengxue Cheng

Shinji Kimura

Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

Test pattern generation for multiple stuck-at faults not covered by test patterns for single faults.

[BibT_eX]

[DOI]

Conrad J. Moore

Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

A new approach for diagnosing bridging faults in logic designs.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

Instruction-based self-test for delay faults maximizing operating temperature.

[BibT_eX]

[DOI]

Proceedings of the 23rd IEEE International Symposium on On-Line Testing and Robust System Design, 2017

Distributed Particle-Based Rendering Framework for Large Data Visualization on HPC Environments.

[BibT_eX]

[DOI]

Proceedings of the 2017 International Conference on High Performance Computing & Simulation, 2017

An approach to approximate computing: Logic transformations for one-minterm changes in specification.

[BibT_eX]

[DOI]

Proceedings of the 2017 IEEE International High Level Design Validation and Test Workshop, 2017

RTL level trace signal selection and coverage estimation during post-silicon validation.

[BibT_eX]

[DOI]

Proceedings of the 2017 IEEE International High Level Design Validation and Test Workshop, 2017

Combining Restorability and Error Detection Ability for Effective Trace Signal Selection.

[BibT_eX]

[DOI]

Proceedings of the on Great Lakes Symposium on VLSI 2017, 2017

DNetSpec: A Distributed Network Testing Toolset for Middleware Developers.

[BibT_eX]

[DOI]

Shintaro Ishihara

Toyokazu Akiyama

Proceedings of the 41st IEEE Annual Computer Software and Applications Conference, 2017

Dissemination of edge-heavy data on heterogeneous MQTT brokers.

[BibT_eX]

[DOI]

Proceedings of the 6th IEEE International Conference on Cloud Networking, 2017

Directcha-maze: A Study of CAPTCHA Configuration with Machine Learning and Brute-Force Attack Defensibility Along with User Convenience Consideration.

[BibT_eX]

[DOI]

Ayane Sano

Proceedings of the Advances on Broad-Band Wireless Computing, 2017

Post Silicon Debugging of Electrical Bugs Using Trace Buffers.

[BibT_eX]

[DOI]

Kentaro Iwata

Mehdi Baradaran Tahoori

Proceedings of the 26th IEEE Asian Test Symposium, 2017

2016

Fast and Efficient Signature-Based Sub-Circuit Matching.

[BibT_eX]

[DOI]

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2016

Embedded memory and ARM Cortex-M0 core using 60-nm C-axis aligned crystalline indium-gallium-zinc oxide FET integrated with 65-nm Si CMOS.

[BibT_eX]

[DOI]

Proceedings of the 2016 IEEE Symposium on VLSI Circuits, 2016

Two axes orthogonal drive transmission for omnidirectional crawler with surface contact.

[BibT_eX]

[DOI]

Proceedings of the 2016 IEEE International Symposium on Safety, 2016

Variable inner volume mechanism for soft and robust gripping - Improvement of gripping performance for large-object gripping.

[BibT_eX]

[DOI]

Proceedings of the 2016 IEEE International Symposium on Safety, 2016

Study on relationship between user awareness and QoE in communication delay on smartphones.

[BibT_eX]

[DOI]

Proceedings of the 14th Annual Conference on Privacy, Security and Trust, 2016

Directcha: A proposal of spatiometric mental rotation CAPTCHA.

[BibT_eX]

[DOI]

Ayane Sano

Proceedings of the 14th Annual Conference on Privacy, Security and Trust, 2016

A Micro Biometric Authentication Mechanism Considering Minute Patterns of the Human Body: A Proposal and the First Attempt.

[BibT_eX]

[DOI]

Proceedings of the 19th International Conference on Network-Based Information Systems, 2016

Automatically adjusting system level designs after RTL/gate-level ECO.

[BibT_eX]

[DOI]

Proceedings of the IEEE International High Level Design Validation and Test Workshop, 2016

Specification by existing design plus use-cases.

[BibT_eX]

[DOI]

Proceedings of the IEEE International High Level Design Validation and Test Workshop, 2016

Secure Communication Protocol Between a Human and a Bank Server for Preventing Man-in-the-Browser Attacks.

[BibT_eX]

[DOI]

Proceedings of the Human Aspects of Information Security, Privacy, and Trust, 2016

Implementation and Initial Evaluation of Game in Which Password Enhancement Factor is Embedded.

[BibT_eX]

[DOI]

Mako Yamada

Proceedings of the HCI International 2016 - Posters' Extended Abstracts, 2016

Synthesizing and Completely Testing Hardware Based on Templates Through Small Numbers of Test Patterns.

[BibT_eX]

[DOI]

Proceedings of the Automated Technology for Verification and Analysis, 2016

A New Approach for Debugging Logic Circuits without Explicitly Debugging Their Functionality.

[BibT_eX]

[DOI]

Proceedings of the 25th IEEE Asian Test Symposium, 2016

Formally analyzing fault tolerance in datapath designs using equivalence checking.

[BibT_eX]

[DOI]

Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016

2015

A Boosting Pass Gate With Improved Switching Characteristics and No Overdriving for Programmable Routing Switch Based on Crystalline In-Ga-Zn-O Technology.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2015

Automatic High-Level Data-Flow Synthesis and Optimization of Polynomial Datapaths Using Functional Decomposition.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2015

Toward Unification of Synthesis and Verification in Topologically Constrained Logic Design.

[BibT_eX]

[DOI]

Proc. IEEE, 2015

Normally-Off Computing for Crystalline Oxide Semiconductor-Based Multicontext FPGA Capable of Fine-Grained Power Gating on Programmable Logic Element With Nonvolatile Shadow Register.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2015

Direct simulation of drying colloidal suspension on substrate using immersed free surface model.

[BibT_eX]

[DOI]

Osamu Koike

Yukio Yamaguchi

J. Comput. Phys., 2015

UPF-based formal verification of low power techniques in modern processors.

[BibT_eX]

[DOI]

Reza Sharafinejad

Proceedings of the 33rd IEEE VLSI Test Symposium, 2015

Efficient signature-based sub-circuit matching.

[BibT_eX]

[DOI]

Proceedings of the 2015 IFIP/IEEE International Conference on Very Large Scale Integration, 2015

Delay Testing Based on Multiple Faulty Behaviors.

[BibT_eX]

[DOI]

Proceedings of the VLSI-SoC: Design for Reliability, Security, and Low Power, 2015

Analysis and testing on delays with two time frames.

[BibT_eX]

[DOI]

Proceedings of the 2015 IFIP/IEEE International Conference on Very Large Scale Integration, 2015

Trace signal selection methods for post silicon debugging.

[BibT_eX]

[DOI]

Shridhar Choudhary

Proceedings of the 2015 IFIP/IEEE International Conference on Very Large Scale Integration, 2015

Physical trust-based persistent authentication.

[BibT_eX]

[DOI]

Christian Damsgaard Jensen

Shiori Arimura

Yuki Ikeya

Proceedings of the 13th Annual Conference on Privacy, Security and Trust, 2015

An Attempt to Memorize Strong Passwords while Playing Games.

[BibT_eX]

[DOI]

Proceedings of the 18th International Conference on Network-Based Information Systems, 2015

Logic analysis and optimization with quick identification of invariants through one time frame analysis.

[BibT_eX]

[DOI]

Proceedings of the 13. ACM/IEEE International Conference on Formal Methods and Models for Codesign, 2015

Hardware in loop testing of an insulin pump.

[BibT_eX]

[DOI]

Sriram Karunagaran

Karuna P. Sahoo

Proceedings of the 2015 IEEE International Test Conference, 2015

16.9 A 128kb 4b/cell nonvolatile memory with crystalline In-Ga-Zn oxide FET using Vt, cancel write method.

[BibT_eX]

[DOI]

Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015

Incremental ATPG methods for multiple faults under multiple fault models.

[BibT_eX]

[DOI]

Proceedings of the Sixteenth International Symposium on Quality Electronic Design, 2015

234 scheduling of 3-2 and 2-1 eliminations for parallel image compositing using non-power-of-two number of processes.

[BibT_eX]

[DOI]

Jorji Nonaka

Kenji Ono

Proceedings of the 2015 International Conference on High Performance Computing & Simulation, 2015

Automatic identification of assertions and invariants with small numbers of test vectors.

[BibT_eX]

[DOI]

Proceedings of the 33rd IEEE International Conference on Computer Design, 2015

Chimera CAPTCHA: A Proposal of CAPTCHA Using Strangeness in Merged Objects.

[BibT_eX]

[DOI]

Proceedings of the Human Aspects of Information Security, Privacy, and Trust, 2015

On Implementation of LUT with Large Numbers of Inputs (Abstract Only).

[BibT_eX]

[DOI]

Proceedings of the 2015 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2015

Temperature-aware software-based self-testing for delay faults.

[BibT_eX]

[DOI]

Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

Detection of test Patterns with Unreachable States through Efficient Inductive-Invariant Identification.

[BibT_eX]

[DOI]

Maria D. Ferraris Araneta

Proceedings of the 24th IEEE Asian Test Symposium, 2015

2014

In vitro and in vivo evaluation of 11C-SD5024, a novel PET radioligand for human brain imaging of cannabinoid CB1 receptors.

[BibT_eX]

[DOI]

NeuroImage, 2014

Retest imaging of [11C]NOP-1A binding to nociceptin/orphanin FQ peptide (NOP) receptors in the brain of healthy humans.

[BibT_eX]

[DOI]

Talakad G. Lohith

Sami S. Zoghbi

Cheryl L. Morse

NeuroImage, 2014

Embedded SRAM and Cortex-M0 Core Using a 60-nm Crystalline Oxide Semiconductor.

[BibT_eX]

[DOI]

IEEE Micro, 2014

SAT-based Automatic Rectification and Debugging of Combinational Circuits with LUT Insertions.

[BibT_eX]

[DOI]

IPSJ Trans. Syst. LSI Des. Methodol., 2014

An Energy-Efficient Patchable Accelerator and Its Design Methods.

[BibT_eX]

[DOI]

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2014

Automatic Rectification of Processor Design Bugs Using a Scalable and General Correction Model.

[BibT_eX]

[DOI]

IEICE Trans. Inf. Syst., 2014

A 32-bit CPU with zero standby power and 1.5-clock sleep/2.5-clock wake-up achieved by utilizing a 180-nm C-axis aligned crystalline In-Ga-Zn oxide transistor.

[BibT_eX]

[DOI]

Proceedings of the Symposium on VLSI Circuits, 2014

Logic synthesis and verification on fixed topology.

[BibT_eX]

[DOI]

Alan Mishchenko

Proceedings of the 22nd International Conference on Very Large Scale Integration, 2014

MAESTRO: A time-driven embedded testbed Architecture with Event-driven Synchronization.

[BibT_eX]

[DOI]

Proceedings of the 20th IEEE Real-Time and Embedded Technology and Applications Symposium, 2014

i/k-Contact: A context-aware user authentication using physical social trust.

[BibT_eX]

[DOI]

Proceedings of the 2014 Twelfth Annual International Conference on Privacy, 2014

Efficient SAT-based ATPG techniques for all multiple stuck-at faults.

[BibT_eX]

[DOI]

Alan Mishchenko

Proceedings of the 2014 International Test Conference, 2014

Variation-Aware Analysis and Test Pattern Generation Based on Functional Faults.

[BibT_eX]

[DOI]

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2014

30.9 Normally-off computing with crystalline InGaZnO-based FPGA.

[BibT_eX]

[DOI]

Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014

Specification and formal verification of power gating in processors.

[BibT_eX]

[DOI]

Proceedings of the Fifteenth International Symposium on Quality Electronic Design, 2014

RTL datapath optimization using system-level transformations.

[BibT_eX]

[DOI]

Proceedings of the Fifteenth International Symposium on Quality Electronic Design, 2014

Multi-step image compositing for massively parallel rendering.

[BibT_eX]

[DOI]

Jorji Nonaka

Kenji Ono

Proceedings of the International Conference on High Performance Computing & Simulation, 2014

An Image-Based CAPTCHA Using Sophisticated Mental Rotation.

[BibT_eX]

[DOI]

Proceedings of the Human Aspects of Information Security, Privacy, and Trust, 2014

Improving polynomial datapath debugging with HEDs.

[BibT_eX]

[DOI]

Somayeh Sadeghi Kohan

Proceedings of the 19th IEEE European Test Symposium, 2014

Embedded SRAM and Cortex-M0 core with backup circuits using a 60-nm crystalline oxide semiconductor for power gating.

[BibT_eX]

[DOI]

Proceedings of the 2014 IEEE Symposium on Low-Power and High-Speed Chips, 2014

2013

On the integration of model-driven design and dynamic assertion-based verification for embedded software.

[BibT_eX]

[DOI]

J. Syst. Softw., 2013

Special session 4B: Elevator talks.

[BibT_eX]

[DOI]

Proceedings of the 31st IEEE VLSI Test Symposium, 2013

Tutorial T10: Post - Silicon Validation, Debug and Diagnosis.

[BibT_eX]

[DOI]

Proceedings of the 26th International Conference on VLSI Design and 12th International Conference on Embedded Systems, 2013

Debugging Methods Through Identification of Appropriate Functions for Internal Gates.

[BibT_eX]

[DOI]

Kosuke Oshima

Proceedings of the VLSI-SoC: At the Crossroads of Emerging Trends, 2013

A debugging method for gate level circuit designs by introducing programmability.

[BibT_eX]

[DOI]

Kosuke Oshima

Proceedings of the 21st IEEE/IFIP International Conference on VLSI and System-on-Chip, 2013

FOF: Functionally Observable Fault and its ATPG techniques.

[BibT_eX]

[DOI]

Proceedings of the 21st IEEE/IFIP International Conference on VLSI and System-on-Chip, 2013

Hardware implementation of BLTL property checkers for acceleration of statistical model checking.

[BibT_eX]

[DOI]

Kosuke Oshima

Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2013

Partial synthesis through sampling with and without specification.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2013

Fast simulation of Digital Spiking Silicon Neuron model employing reconfigurable dataflow computing.

[BibT_eX]

[DOI]

Proceedings of the 2013 International Conference on Field-Programmable Technology, 2013

Debugging processors with advanced features by reprogramming LUTs on FPGA.

[BibT_eX]

[DOI]

Proceedings of the 2013 International Conference on Field-Programmable Technology, 2013

Rectification of advanced microprocessors without changing routing on FPGAs (abstract only).

[BibT_eX]

[DOI]

Proceedings of the 2013 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2013

2012

Population-based input function and image-derived input function for [11C](R)-rolipram PET imaging: Methodology, validation and application to the study of major depressive disorder.

[BibT_eX]

[DOI]

NeuroImage, 2012

Quantification of metabotropic glutamate subtype 5 receptors in the brain by an equilibrium method using 18F-SP203.

[BibT_eX]

[DOI]

NeuroImage, 2012

Transaction Ordering in Network-on-Chips for Post-Silicon Validation.

[BibT_eX]

[DOI]

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2012

Time-Constraint-Aware Optimization of Assertions in Embedded Software.

[BibT_eX]

[DOI]

Viacheslav Izosimov

J. Electron. Test., 2012

Verifying Reliability (Dagstuhl Seminar 12341).

[BibT_eX]

[DOI]

Görschwin Fey

Natasa Miskov-Zivanov

Kaushik Roy

Matteo Sonza Reorda

Dagstuhl Reports, 2012

An efficient method to localize and correct bugs in high-level designs using counterexamples and potential dependence.

[BibT_eX]

[DOI]

Shohei Ono

Proceedings of the 20th IEEE/IFIP International Conference on VLSI and System-on-Chip, 2012

SEU Tolerant Robust Latch Design.

[BibT_eX]

[DOI]

Proceedings of the Progress in VLSI Design and Test - 16th International Symposium, 2012

Distance aware ray tracing for curves.

[BibT_eX]

[DOI]

Koji Nakamaru

Toru Matsuoka

Proceedings of the International Conference on Computer Graphics and Interactive Techniques, 2012

Future direction of digital content: 20th anniversary keynote talk.

[BibT_eX]

[DOI]

Proceedings of the 20th ACM Multimedia Conference, MM '12, Nara, Japan, October 29, 2012

Polynomial datapath synthesis and optimization based on vanishing polynomial over Z2m and algebraic techniques.

[BibT_eX]

[DOI]

Proceedings of the Tenth ACM/IEEE International Conference on Formal Methods and Models for Codesign, 2012

Transaction-based post-silicon debug of many-core System-on-Chips.

[BibT_eX]

[DOI]

Proceedings of the Thirteenth International Symposium on Quality Electronic Design, 2012

SEU tolerant robust memory cell design.

[BibT_eX]

[DOI]

Proceedings of the 18th IEEE International On-Line Testing Symposium, 2012

Automatic assertion extraction in gate-level simulation using GPGPUs.

[BibT_eX]

[DOI]

Shohei Ono

Proceedings of the 30th International IEEE Conference on Computer Design, 2012

Post-silicon verification and debugging with control flow traces and patchable hardware.

[BibT_eX]

[DOI]

Proceedings of the 2012 IEEE International High Level Design Validation and Test Workshop, 2012

A functional test generation technique for RTL datapaths.

[BibT_eX]

[DOI]

Proceedings of the 2012 IEEE International High Level Design Validation and Test Workshop, 2012

Automatic rectification of design errors in complex processors with programmable hardware.

[BibT_eX]

[DOI]

Proceedings of the 2012 International Conference on Field-Programmable Technology, 2012

Post-silicon debugging targeting electrical errors with patchable controllers (abstract only).

[BibT_eX]

[DOI]

Proceedings of the ACM/SIGDA 20th International Symposium on Field Programmable Gate Arrays, 2012

Simulation-Based Analysis of Cyberphysical Systems.

[BibT_eX]

[DOI]

Proceedings of the 15th Euromicro Conference on Digital System Design, 2012

Dynamic property mining for embedded software.

[BibT_eX]

[DOI]

Marco Bonato

Franco Fummi

Graziano Pravadelli

Proceedings of the 10th International Conference on Hardware/Software Codesign and System Synthesis, 2012

Error Model Free Automatic Design Error Correction of Complex Processors Using Formal Methods.

[BibT_eX]

[DOI]

Proceedings of the 21st IEEE Asian Test Symposium, 2012

Automated data analysis techniques for a modern silicon debug environment.

[BibT_eX]

[DOI]

Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012

On error tolerance and Engineering Change with Partially Programmable Circuits.

[BibT_eX]

[DOI]

Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012

Post-silicon patching for verification/debugging with high-level models and programmable logic.

[BibT_eX]

[DOI]

Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012

2011

Kinetic analysis in human brain of [11C](R)-rolipram, a positron emission tomographic radioligand to image phosphodiesterase 4: A retest study and use of an image-derived input function.

[BibT_eX]

[DOI]

NeuroImage, 2011

Exact Minimum Factoring of Incompletely Specified Logic Functions via Quantified Boolean Satisfiability.

[BibT_eX]

[DOI]

IPSJ Trans. Syst. LSI Des. Methodol., 2011

Data Flow Graph Partitioning Algorithms and Their Evaluations for Optimal Spatio-temporal Computation on a Coarse Grain Reconfigurable Architecture.

[BibT_eX]

[DOI]

IPSJ Trans. Syst. LSI Des. Methodol., 2011

Multi-Level Bounded Model Checking with Symbolic Counterexamples.

[BibT_eX]

[DOI]

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2011

An Automatic Method of Mapping I/O Sequences of Chip Execution onto High-level Design for Post-Silicon Debugging.

[BibT_eX]

[DOI]

Yeonbok Lee

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2011

Tutorial: "Post silicon debug of SOC designs".

[BibT_eX]

[DOI]

Proceedings of the IEEE 24th International SoC Conference, SOCC 2011, Taipei, Taiwan, 2011

EFSM-based model-driven approach to concolic testing of system-level design.

[BibT_eX]

[DOI]

Proceedings of the 9th IEEE/ACM International Conference on Formal Methods and Models for Codesign, 2011

SEU tolerant SRAM cell.

[BibT_eX]

[DOI]

Proceedings of the 12th International Symposium on Quality Electronic Design, 2011

Global transaction ordering in Network-on-Chips for post-silicon validation.

[BibT_eX]

[DOI]

Proceedings of the 12th International Symposium on Quality Electronic Design, 2011

Debugging and optimizing high performance superscalar out-of-order processors using formal verification techniques.

[BibT_eX]

[DOI]

Proceedings of the 12th International Symposium on Quality Electronic Design, 2011

Early case splitting and false path detection to improve high level ATPG techniques.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

Automated System Testing of Dynamic Web Applications.

[BibT_eX]

[DOI]

Proceedings of the Software and Data Technologies - 6th International Conference, 2011

Client-tier Validation of Dynamic Web Applications.

[BibT_eX]

Proceedings of the ICSOFT 2011, 2011

Model-driven design and validation of embedded software.

[BibT_eX]

[DOI]

Proceedings of the 6th International Workshop on Automation of Software Test, 2011

Formal verification guided automatic design error diagnosis and correction of complex processors.

[BibT_eX]

[DOI]

Proceedings of the 2011 IEEE International High Level Design Validation and Test Workshop, 2011

Modular equivalence verification of polynomial datapaths with multiple word-length operands.

[BibT_eX]

[DOI]

Proceedings of the 2011 IEEE International High Level Design Validation and Test Workshop, 2011

Interconnect-topology independent mapping algorithm for a Coarse Grained Reconfigurable Architecture.

[BibT_eX]

[DOI]

Proceedings of the 2011 International Conference on Field-Programmable Technology, 2011

Optimization of Assertion Placement in Time-Constrained Embedded Systems.

[BibT_eX]

[DOI]

Proceedings of the 16th European Test Symposium, 2011

An energy-efficient patchable accelerator for post-silicon engineering changes.

[BibT_eX]

[DOI]

Proceedings of the 9th International Conference on Hardware/Software Codesign and System Synthesis, 2011

Synthesizing, Verifying, and Debugging SoC with FSM-Based Specification of On-Chip Communication Protocols.

[BibT_eX]

[DOI]

Proceedings of the Automated Technology for Verification and Analysis, 2011

High Level Verification and Its Use at Pos-Silicon Debugging and Patching.

[BibT_eX]

[DOI]

Proceedings of the 20th IEEE Asian Test Symposium, 2011

On-chip dynamic signal sequence slicing for efficient post-silicon debugging.

[BibT_eX]

[DOI]

Yeonbok Lee

Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011

Utilizing high level design information to speed up post-silicon debugging.

[BibT_eX]

[DOI]

Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011

Dataflow Graph Partitioning for Optimal Spatio-Temporal Computation on a Coarse Grain Reconfigurable Architecture.

[BibT_eX]

[DOI]

Proceedings of the Reconfigurable Computing: Architectures, Tools and Applications, 2011

Accelerating Tsunami simulation with FPGA and GPU through automatic compilation.

[BibT_eX]

[DOI]

Proceedings of the 1st International Conference on Wireless Technologies for Humanitarian Relief, 2011

2010

Coverage Driven High-Level Test Generation Using a Polynomial Model of Sequential Circuits.

[BibT_eX]

[DOI]

Mohammad Mirzaei

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010

Modular Datapath Optimization and Verification Based on Modular-HED.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010

Category: Methodology: Quantification and test-retest study of 11C-(R)-rolipram, a PET tracer of the cAMP cascade, using an arterial input function and an image-derived input function.

[BibT_eX]

[DOI]

NeuroImage, 2010

Image-derived input function for brain imaging using the high-resolution research tomograph.

[BibT_eX]

[DOI]

NeuroImage, 2010

Comparison of [11C]-(R)-PK 11195 and [11C]PBR28, two radioligands for translocator protein (18 kDa) in human and monkey: Implications for positron emission tomographic imaging of this inflammation biomarker.

[BibT_eX]

[DOI]

NeuroImage, 2010

Changes of brain phosphodiesterase 4 in major depression.

[BibT_eX]

[DOI]

NeuroImage, 2010

Performance-Constrained Transistor Sizing for Different Cell Count Minimization.

[BibT_eX]

[DOI]

J. Inf. Process., 2010

Custom Instruction Generation for Configurable Processors with Limited Numbers of Operands.

[BibT_eX]

[DOI]

Kenshu Seto

IPSJ Trans. Syst. LSI Des. Methodol., 2010

Performance Estimation with Automatic False-Path Detection for System-Level Designs.

[BibT_eX]

[DOI]

IPSJ Trans. Syst. LSI Des. Methodol., 2010

DNA-grafted-polymer mediated self-assembly of micro components.

[BibT_eX]

[DOI]

Proceedings of the 5th IEEE International Conference on Nano/Micro Engineered and Molecular Systems, 2010

Synthesis and formal verification of on-chip protocol transducers through decomposed specification.

[BibT_eX]

[DOI]

Proceedings of the 11th International Symposium on Quality of Electronic Design (ISQED 2010), 2010

Generation of I/O sequences for a high-level design from those in post-silicon for efficient post-silicon debugging.

[BibT_eX]

[DOI]

Yeonbok Lee

Proceedings of the 28th International Conference on Computer Design, 2010

Polynomial datapath optimization using constraint solving and formal modelling.

[BibT_eX]

[DOI]

Proceedings of the 2010 International Conference on Computer-Aided Design, 2010

SEU tolerant SRAM for FPGA applications.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Field-Programmable Technology, 2010

A debugging method for repairing post-silicon bugs of high performance processors in the fields.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Field-Programmable Technology, 2010

Aggressive overclocking support using a novel timing error recovery technique on FPGAs (abstract only).

[BibT_eX]

[DOI]

Proceedings of the ACM/SIGDA 18th International Symposium on Field Programmable Gate Arrays, 2010

Towards minimizing execution delays on dynamically reconfigurable processors: a case study on REDEFINE.

[BibT_eX]

[DOI]

Proceedings of the 2010 International Conference on Compilers, 2010

Guided gate-level ATPG for sequential circuits using a high-level test generation approach.

[BibT_eX]

[DOI]

Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010

Pipelined Microprocessors Optimization and Debugging.

[BibT_eX]

[DOI]

Proceedings of the Reconfigurable Computing: Architectures, 2010

2009

A Formal Approach for Debugging Arithmetic Circuits.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009

Trends in Formal Verification Techniques for C-based Hardware Designs.

[BibT_eX]

[DOI]

IPSJ Trans. Syst. LSI Des. Methodol., 2009

Word-Level Equivalence Checking in Bit-Level Accuracy by Synthesizing Designs onto Identical Datapath.

[BibT_eX]

[DOI]

IEICE Trans. Inf. Syst., 2009

Interconnect-Aware Pipeline Synthesis for Array-Based Architectures.

[BibT_eX]

[DOI]

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009

A Unified Framework for Equivalence Verification of Datapath Oriented Applications.

[BibT_eX]

[DOI]

IEICE Trans. Inf. Syst., 2009

Functional Equivalence Verification Tools in High-Level Synthesis Flows.

[BibT_eX]

[DOI]

IEEE Des. Test Comput., 2009

Intelligence Dynamics: a concept and preliminary experiments for open-ended learning agents.

[BibT_eX]

[DOI]

Auton. Agents Multi Agent Syst., 2009

High-level optimization of integer multipliers over a finite bit-width with verification capabilities.

[BibT_eX]

[DOI]

Proceedings of the 7th ACM/IEEE International Conference on Formal Methods and Models for Codesign (MEMOCODE 2009), 2009

Improving the accuracy of rule-based equivalence checking of system-level design descriptions by identifying potential internal equivalences.

[BibT_eX]

[DOI]

Proceedings of the 10th International Symposium on Quality of Electronic Design (ISQED 2009), 2009

Transaction-based debugging of system-on-chips with patterns.

[BibT_eX]

[DOI]

Proceedings of the 27th International Conference on Computer Design, 2009

Improved heuristics for finite word-length polynomial datapath optimization.

[BibT_eX]

[DOI]

Proceedings of the 2009 International Conference on Computer-Aided Design, 2009

Modular arithmetic decision procedure with auto-correction mechanism.

[BibT_eX]

[DOI]

Proceedings of the IEEE International High Level Design Validation and Test Workshop, 2009

09461 Abstracts Collection - Algorithms and Applications for Next Generation SAT Solvers.

[BibT_eX]

[DOI]

Proceedings of the Algorithms and Applications for Next Generation SAT Solvers, 08.11., 2009

Polynomial datapath optimization using partitioning and compensation heuristics.

[BibT_eX]

[DOI]

Omid Sarbishei

Proceedings of the 46th Design Automation Conference, 2009

Debugging from high level down to gate level.

[BibT_eX]

[DOI]

Yoshihisa Kojima

Proceedings of the 46th Design Automation Conference, 2009

A Post-Silicon Debug Support Using High-Level Design Description.

[BibT_eX]

[DOI]

Proceedings of the Eighteentgh Asian Test Symposium, 2009

2008

Brain and whole-body imaging in nonhuman primates of [11C]PBR28, a promising PET radioligand for peripheral benzodiazepine receptors.

[BibT_eX]

[DOI]

NeuroImage, 2008

Kinetic analysis in healthy humans of a novel positron emission tomography radioligand to image the peripheral benzodiazepine receptor, a potential biomarker for inflammation.

[BibT_eX]

[DOI]

NeuroImage, 2008

Dependence Graph Based Verification and Synthesis of Hardware/Software Co-Designs with SAT Related Formulation.

[BibT_eX]

[DOI]

Kenshu Seto

J. Satisf. Boolean Model. Comput., 2008

3D Perception and Environment Map Generation for Humanoid Robot Navigation.

[BibT_eX]

[DOI]

Int. J. Robotics Res., 2008

Custom Instruction Generation with High-Level Synthesis.

[BibT_eX]

[DOI]

Kenshu Seto

Proceedings of the IEEE Symposium on Application Specific Processors, 2008

Rule-Based Approaches for Equivalence Checking of SpecC Programs.

[BibT_eX]

[DOI]

Subash Shankar

Proceedings of the 6th ACM & IEEE International Conference on Formal Methods and Models for Co-Design (MEMOCODE 2008), 2008

Arithmetic Circuits Verification without Looking for Internal Equivalences.

[BibT_eX]

[DOI]

Omid Sarbishei

Proceedings of the 6th ACM & IEEE International Conference on Formal Methods and Models for Co-Design (MEMOCODE 2008), 2008

Motion control of a virtual humanoid that can perform real physical interactions with a human.

[BibT_eX]

[DOI]

Proceedings of the 2008 IEEE/RSJ International Conference on Intelligent Robots and Systems, 2008

A HW/SW Co-Reuse Methodology Based on Design Refinement Templates in UML Diagrams.

[BibT_eX]

Proceedings of the ICSOFT 2008, 2008

Adaptive grasping by multi fingered hand with tactile sensor based on robust force and position control.

[BibT_eX]

[DOI]

Proceedings of the 2008 IEEE International Conference on Robotics and Automation, 2008

Multi-level Bounded Model Checking to detect bugs beyond the bound.

[BibT_eX]

[DOI]

Proceedings of the IEEE International High Level Design Validation and Test Workshop, 2008

Performance-Constrained Different Cell Count Minimization for Continuously-Sized Circuits.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2008

Sequential Equivalence Checking Using a Hybrid Boolean-Word Level Decision Diagram.

[BibT_eX]

[DOI]

Proceedings of the Advances in Computer Science and Engineering, 2008

An Interactive Verification and Debugging Environment by Concrete/Symbolic Simulations for System-Level Designs.

[BibT_eX]

[DOI]

Proceedings of the 17th IEEE Asian Test Symposium, 2008

Targeting Leakage Constraints during ATPG.

[BibT_eX]

[DOI]

Proceedings of the 17th IEEE Asian Test Symposium, 2008

Verification Techniques for System-Level Design.

[BibT_eX]

[DOI]

Mukul R. Prasad

The Morgan Kaufmann series in systems on silicon, Morgan Kaufmann, ISBN: 978-0-12-370616-4, 2008

2007

Corrigendum to "Quantification of brain phosphodiesterase 4 in rat with (R)-[11C]rolipram-PET" [NeuroImage 26 (2005) 1201-1210].

[BibT_eX]

[DOI]

NeuroImage, 2007

Hardware/Software Co-design and Verification Methodology from System Level Based on System Dependence Graph.

[BibT_eX]

[DOI]

J. Univers. Comput. Sci., 2007

Multiscale simulation method for self-organization of nanoparticles in dense suspension.

[BibT_eX]

[DOI]

Yukio Yamaguchi

J. Comput. Phys., 2007

VLSI CAD Education and Exercise Course with Public Domain Tools.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference on Microelectronic Systems Education, 2007

Lateral State Prediction for Automated Steering using Reliability-Weighted Measurements from Multiple Sensors.

[BibT_eX]

[DOI]

Makoto Aso

Keitaro Niki

Proceedings of the IEEE Intelligent Transportation Systems Conference, 2007

Interconnect-aware Pipeline Synthesis for Array based Reconfigurable Architectures.

[BibT_eX]

[DOI]

Proceedings of the Embedded System Design: Topics, Techniques and Trends, IFIP TC10 Working Conference: International Embedded Systems Symposium (IESS), May 30, 2007

A novel formal approach to generate high-level test vectors without ILP and SAT solvers.

[BibT_eX]

[DOI]

Proceedings of the IEEE International High Level Design Validation and Test Workshop, 2007

Development and Verification of a Collaborative Printing Environment.

[BibT_eX]

[DOI]

Proceedings of the Fifth International Conference on Creating, 2007

Using Counterexample Analysis to Minimize the Number of Predicates for Predicate Abstraction.

[BibT_eX]

[DOI]

Proceedings of the Automated Technology for Verification and Analysis, 2007

Automatic Merge-Point Detection for Sequential Equivalence Checking of System-Level and RTL Descriptions.

[BibT_eX]

[DOI]

Proceedings of the Automated Technology for Verification and Analysis, 2007

Protocol Transducer Synthesis using Divide and Conquer approach.

[BibT_eX]

[DOI]

Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007

2006

Embedded Software Verification Using Symbolic Execution and Uninterpreted Functions.

[BibT_eX]

[DOI]

Int. J. Parallel Program., 2006

Synchronization Verification in System-Level Design with ILP Solvers.

[BibT_eX]

[DOI]

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2006

The AMS Extension to System Level Design Language - SpecC.

[BibT_eX]

[DOI]

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2006

Synchronization Mechanism for Timed/Untimed Mixed-Signal System Level Design Environment.

[BibT_eX]

[DOI]

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2006

Sequential Equivalence Checking.

[BibT_eX]

[DOI]

Proceedings of the 19th International Conference on VLSI Design (VLSI Design 2006), 2006

Equivalence checking: a rule-based approach.

[BibT_eX]

[DOI]

Subash Shankar

Sasaki Shunsuke

Proceedings of the 4th ACM & IEEE International Conference on Formal Methods and Models for Co-Design (MEMOCODE 2006), 2006

Equivalence Checking of C Programs by Locally Performing Symbolic Simulation on Dependence Graphs.

[BibT_eX]

[DOI]

Hiroshi Saito

Proceedings of the 7th International Symposium on Quality of Electronic Design (ISQED 2006), 2006

An optimization of bus interconnects pitch for low-power and reliable bus encoding scheme.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

Equivalence Checking with Rule-Based Equivalence Propagation and High-Level Synthesis.

[BibT_eX]

[DOI]

Proceedings of the Eleventh Annual IEEE International High-Level Design Validation and Test Workshop 2006, 2006

Dynamically reconfigurable protocol transducer.

[BibT_eX]

[DOI]

Proceedings of the 2006 IEEE International Conference on Field Programmable Technology, 2006

System LSI distributed collaborative design environment for both designers and CAD developers/engineers.

[BibT_eX]

[DOI]

Daisuke Ando

Proceedings of the Fourth International Conference on Creating, 2006

Object-oriented analysis and specification for HW/SW co-design with UML diagrams.

[BibT_eX]

Ken Matsui

Proceedings of the IASTED International Conference on Advances in Computer Science and Technology, 2006

2005

Autonomous evolution of dynamic gaits with two quadruped robots.

[BibT_eX]

[DOI]

IEEE Trans. Robotics, 2005

Equivalence checking between behavioral and RTL descriptions with virtual controllers and datapaths.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2005

Quantification of brain phosphodiesterase 4 in rat with (R)-[11C]Rolipram-PET.

[BibT_eX]

[DOI]

NeuroImage, 2005

An Equivalence Checking Method for C Descriptions Based on Symbolic Simulation with Textual Differences.

[BibT_eX]

[DOI]

Hiroshi Saito

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2005

Low Power and Fault Tolerant Encoding Methods for On-Chip Data Transfer in Practical Applications.

[BibT_eX]

[DOI]

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2005

Slicing-based Hardware/Software Co-design Methodology From Functional Specifications.

[BibT_eX]

[DOI]

Shunsuke Sasaki

Proceedings of the First IPM International Workshop on Foundations of Software Engineering, 2005

Extended abstract: a formal design approach from software oriented UML descriptions to hardware oriented RTL.

[BibT_eX]

[DOI]

Proceedings of the 3rd ACM & IEEE International Conference on Formal Methods and Models for Co-Design (MEMOCODE 2005), 2005

Object-oriented analysis and design of hardware/software co-designs with dependence analysis for design reuse.

[BibT_eX]

[DOI]

Shunsuke Sasaki

Ken Matsui

Proceedings of the 2005 IEEE International Conference on Information Reuse and Integration, 2005

Real-Time Path Planning for Humanoid Robot Navigation.

[BibT_eX]

[DOI]

Proceedings of the IJCAI-05, Proceedings of the Nineteenth International Joint Conference on Artificial Intelligence, Edinburgh, Scotland, UK, July 30, 2005

A Floor and Obstacle Height Map for 3D Navigation of a Humanoid Robot.

[BibT_eX]

[DOI]

Proceedings of the 2005 IEEE International Conference on Robotics and Automation, 2005

A modular architecture for humanoid robot navigation.

[BibT_eX]

[DOI]

Proceedings of the 5th IEEE-RAS International Conference on Humanoid Robots, 2005

System level design language extensions for timed/untimed digital-analog combined system design.

[BibT_eX]

[DOI]

Proceedings of the 15th ACM Great Lakes Symposium on VLSI 2005, 2005

Pipeline Scheduling for Array Based Reconfigurable Architectures Considering Interconnect Delays.

[BibT_eX]

Proceedings of the 2005 IEEE International Conference on Field-Programmable Technology, 2005

AMS Extensions for Timed/Untimed System-Level Design Language.

[BibT_eX]

[DOI]

Proceedings of the Forum on specification and Design Languages, 2005

Hexagonal storage scheme for interleaved frame buffers and textures.

[BibT_eX]

[DOI]

Yosuke Bando

Takahiro Saito

Proceedings of the ACM SIGGRAPH/EUROGRAPHICS Symposium on Graphics Hardware 2005, 2005

Behavior-RTL Equivalence Checking Based on Data Transfer Analysis with Virtual Controllers and Datapaths.

[BibT_eX]

[DOI]

Proceedings of the Correct Hardware Design and Verification Methods, 2005

2004

On activating human communications with pet-type robot AIBO.

[BibT_eX]

[DOI]

Proc. IEEE, 2004

High Level Design Validation: Current Practices and Future Directions.

[BibT_eX]

[DOI]

Proceedings of the 17th International Conference on VLSI Design (VLSI Design 2004), 2004

Formal Verification of C Language Based VLSI Designs.

[BibT_eX]

[DOI]

Proceedings of the 17th International Conference on VLSI Design (VLSI Design 2004), 2004

Associated Emotion and Its Expression in an Entertainment Robot QRIO.

[BibT_eX]

[DOI]

Proceedings of the Entertainment Computing, 2004

Behavior selection and motion modulation in emotionally grounded architecture for QRIO SDR-4XII.

[BibT_eX]

[DOI]

Tsutomu Sawada

Tsuyoshi Takagi

Proceedings of the 2004 IEEE/RSJ International Conference on Intelligent Robots and Systems, Sendai, Japan, September 28, 2004

Stair climbing for humanoid robots using stereo vision.

[BibT_eX]

[DOI]

Proceedings of the 2004 IEEE/RSJ International Conference on Intelligent Robots and Systems, Sendai, Japan, September 28, 2004

Behavior Description and Control using Behavior Module for Personal Robot.

[BibT_eX]

[DOI]

Proceedings of the 2004 IEEE International Conference on Robotics and Automation, 2004

Learning behavior selection through interaction based on emotionally grounded symbol concept.

[BibT_eX]

[DOI]

Proceedings of the 4th IEEE/RAS International Conference on Humanoid Robots, 2004

On equivalence checking between behavioral and RTL descriptions.

[BibT_eX]

[DOI]

Proceedings of the Ninth IEEE International High-Level Design Validation and Test Workshop 2004, 2004

Precomputed Radiance Transfer with Spatially-Varying Lighting Effects.

[BibT_eX]

[DOI]

Takashi Kanai

Proceedings of the 2004 International Conference on Computer Graphic, 2004

2003

An ethological and emotional basis for human-robot interaction.

[BibT_eX]

[DOI]

Robotics Auton. Syst., 2003

Verification of Synchronization in SpecC Description with the Use of Difference Decision Diagrams.

[BibT_eX]

[DOI]

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2003

Irredundant Low Power Address Bus Encoding Techniques Based on Adaptive Codebooks.

[BibT_eX]

[DOI]

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2003

An Overview of RoboCup-2002 Fukuoka/Busan.

[BibT_eX]

[DOI]

AI Mag., 2003

High Presence Remote Presentation in the Shared Immersive Virtual World.

[BibT_eX]

[DOI]

Proceedings of the IEEE Virtual Reality Conference 2003 (VR 2003), 2003

Comparative Study On Verilog-Based And C-Based Hardware Design Education.

[BibT_eX]

[DOI]

Proceedings of the 2003 International Conference on Microelectronics Systems Education, 2003

Engineering Changes in Field Modifiable Architectures.

[BibT_eX]

[DOI]

Proceedings of the 1st ACM & IEEE International Conference on Formal Methods and Models for Co-Design (MEMOCODE 2003), 2003

SDR-4X II: A Small Humanoid as an Entertainer in Home Environment.

[BibT_eX]

[DOI]

Proceedings of the Robotics Research, The Eleventh International Symposium, 2003

Autonomous behavior control architecture of entertainment humanoid robot SDR-4X.

[BibT_eX]

[DOI]

Proceedings of the 2003 IEEE/RSJ International Conference on Intelligent Robots and Systems, Las Vegas, Nevada, USA, October 27, 2003

A small biped entertainment robot exploring attractive applications.

[BibT_eX]

[DOI]

Proceedings of the 2003 IEEE International Conference on Robotics and Automation, 2003

Field Modifiable Architecture with FPGAs and its Design/Verification/Debugging Methodologies.

[BibT_eX]

[DOI]

Yoshihisa Kojima

Proceedings of the 36th Hawaii International Conference on System Sciences (HICSS-36 2003), 2003

Model Checking for Dependable Software-Intensive Systems.

[BibT_eX]

[DOI]

Edmund M. Clarke

David P. Gluch

Proceedings of the 2003 International Conference on Dependable Systems and Networks (DSN 2003), 2003

Formal verification - prove it or pitch it.

[BibT_eX]

[DOI]

Proceedings of the 40th Design Automation Conference, 2003

Logic optimization for asynchronous speed independent controllers using transduction method.

[BibT_eX]

[DOI]

Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003

Irredundant address bus encoding techniques based on adaptive codebooks for low power.

[BibT_eX]

[DOI]

Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003

Event-driven observability enhanced coverage analysis of C programs for functional validation.

[BibT_eX]

[DOI]

Farzan Fallah

Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003

2002

Program slicing for VHDL.

[BibT_eX]

[DOI]

Int. J. Softw. Tools Technol. Transf., 2002

RoboCup 2001.

[BibT_eX]

[DOI]

IEEE Robotics Autom. Mag., 2002

The road to RoboCup 2050.

[BibT_eX]

[DOI]

IEEE Robotics Autom. Mag., 2002

A Small Biped Entertainment Robot.

[BibT_eX]

[DOI]

J. Robotics Mechatronics, 2002

Efficient Combinational Verification Using Overlapping Local BDDs and a Hash Table.

[BibT_eX]

[DOI]

Formal Methods Syst. Des., 2002

Simultaneous Circuit Transformation and Routing.

[BibT_eX]

[DOI]

Proceedings of the 7th Asia and South Pacific Design Automation Conference (ASP-DAC 2002), 2002

Sony Four Legged Robot League at RoboCup 2002.

[BibT_eX]

[DOI]

Proceedings of the RoboCup 2002: Robot Soccer World Cup VI, 2002

Formal Verification of a Pipelined Processor with New Memory.

[BibT_eX]

[DOI]

Hiroshi Nakamura

Takanori Arai

Proceedings of the 9th Pacific Rim International Symposium on Dependable Computing (PRDC 2002), 2002

Logic Optimization for Asynchronous SI Controllers using Transduction Method.

[BibT_eX]

Proceedings of the 11th IEEE/ACM International Workshop on Logic & Synthesis, 2002

Field Modifiable Architecture and its Design Methodology: System Design Without Logic Synthesis.

[BibT_eX]

Proceedings of the 11th IEEE/ACM International Workshop on Logic & Synthesis, 2002

An equivalence checking methodology for hardware oriented C-based specifications.

[BibT_eX]

[DOI]

Hiroshi Saito

Takaya Ogawa

Takashi Nanya

Proceedings of the Seventh IEEE International High-Level Design Validation and Test Workshop 2002, 2002

Debug methodology for arithmetic circuits on FPGAs.

[BibT_eX]

[DOI]

Masao Kubo

Proceedings of the 2002 IEEE International Conference on Field-Programmable Technology, 2002

Field modifiable architecture with FPGAs and its design methodology.

[BibT_eX]

[DOI]

Proceedings of the 2002 IEEE International Conference on Field-Programmable Technology, 2002

Verification of Event-Based Synchronization of SpecC Description Using Difference Decision Diagrams.

[BibT_eX]

[DOI]

Proceedings of the Formal Techniques for Networked and Distributed Systems, 2002

Hardware-Assisted Relief Texture Mapping.

[BibT_eX]

[DOI]

Takashi Kanai

Proceedings of the 23rd Annual Conference of the European Association for Computer Graphics, 2002

2001

Automatic test pattern generation for functional register-transferlevel circuits using assignment decision diagrams.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001

A Note on Complexity of OBDD Composition and Efficiency of Partitioned-OBDDs over OBDDs.

[BibT_eX]

[DOI]

Ingo Wegener

IEEE Trans. Computers, 2001

AIBO: Toward the Era of Digital Creatures.

[BibT_eX]

[DOI]

Int. J. Robotics Res., 2001

Multiresolution Interpolation Meshes.

[BibT_eX]

[DOI]

Proceedings of the 9th Pacific Conference on Computer Graphics and Applications, 2001

New Design Paradigms: What Needs to be Standardized?.

[BibT_eX]

[DOI]

Proceedings of the 14th International Symposium on Systems Synthesis, 2001

The standard SpecC language.

[BibT_eX]

[DOI]

Jean-Christophe Bouramoué

Hiroshi Nakamura

Proceedings of the 14th International Symposium on Systems Synthesis, 2001

Motion entertainment by a small humanoid robot based on OPEN-R.

[BibT_eX]

[DOI]

Proceedings of the IEEE/RSJ International Conference on Intelligent Robots and Systems, 2001

Ethological Modeling and Architecture for an Entertainment Robot.

[BibT_eX]

[DOI]

Proceedings of the 2001 IEEE International Conference on Robotics and Automation, 2001

Architecture and preliminary experimental results for emotionally grounded symbol acquisition.

[BibT_eX]

[DOI]

Proceedings of the Fifth International Conference on Autonomous Agents, 2001

2000

Vision, Strategy, and Localization Using the Sony Robots at RoboCup-98.

[BibT_eX]

[DOI]

Pierre Blazevic

AI Mag., 2000

Testing, Verification, and Diagnosis in the Presence of Unknowns.

[BibT_eX]

[DOI]

Proceedings of the 18th IEEE VLSI Test Symposium (VTS 2000), 30 April, 2000

Hierarchical Error Diagnosis Targeting RTL Circuits.

[BibT_eX]

[DOI]

Proceedings of the 13th International Conference on VLSI Design (VLSI Design 2000), 2000

Overview of RoboCup-2000.

[BibT_eX]

[DOI]

Gerhard K. Kraetzschmar

Proceedings of the RoboCup 2000: Robot Soccer World Cup IV, 2000

Progress in RoboCup Soccer Research in 2000.

[BibT_eX]

[DOI]

Proceedings of the Experimental Robotics VII [ISER 2000, 2000

A quadruped robot platform with basic software for RoboCup-99 legged robot league.

[BibT_eX]

[DOI]

Takashi Yamamoto

Proceedings of the IEEE/RSJ International Conference on Intelligent Robots and Systems, 2000

Evolving Robust Gaits with AIBO.

[BibT_eX]

[DOI]

Proceedings of the 2000 IEEE International Conference on Robotics and Automation, 2000

Digital Creatures for Future Entertainment Robotics.

[BibT_eX]

[DOI]

Proceedings of the 2000 IEEE International Conference on Robotics and Automation, 2000

Evolution of Controllers from a High-Level Simulator to a High DOF Robot.

[BibT_eX]

[DOI]

Proceedings of the Evolvable Systems: From Biology to Hardware, 2000

Efficient variable ordering using aBDD based sampling.

[BibT_eX]

[DOI]

Proceedings of the 37th Conference on Design Automation, 2000

Automatic test pattern generation for functional RTL circuits using assignment decision diagrams.

[BibT_eX]

[DOI]

Proceedings of the 37th Conference on Design Automation, 2000

Automatic partitioning for efficient combinatorial verification.

[BibT_eX]

[DOI]

Proceedings of ASP-DAC 2000, 2000

1999

An efficient filter-based approach for combinational verification.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999

A reconfigurable robot platform.

[BibT_eX]

[DOI]

Robotics Auton. Syst., 1999

A Retargetable Compilation Methodology for Embedded Digital Signal Processors Using a Machine-Dependent Code Optimization Library.

[BibT_eX]

[DOI]

Ashok Sudarsanam

Sharad Malik

Des. Autom. Embed. Syst., 1999

On the Evaluation of Arbitrary Defect Coverage of Test Sets.

[BibT_eX]

[DOI]

Proceedings of the 17th IEEE VLSI Test Symposium (VTS '99), 1999

Efficient Scheduling Techniques for ROBDD Construction.

[BibT_eX]

[DOI]

Proceedings of the 12th International Conference on VLSI Design (VLSI Design 1999), 1999

Overview of RoboCup-99.

[BibT_eX]

[DOI]

Manuela M. Veloso

Enrico Pagello

Gerhard K. Kraetzschmar

Proceedings of the RoboCup-99: Robot Soccer World Cup III, 1999

Syntactic-semantic analysis of reconfigurable robot.

[BibT_eX]

[DOI]

Toshitada Doi

Proceedings of the Proceedings 1999 IEEE/RSJ International Conference on Intelligent Robots and Systems. Human and Environment Friendly Robots with High Intelligence and Emotional Quotients, 1999

Speeding Up Look-up-Table Driven Logic Simulation.

[BibT_eX]

Fumiyasu Hirose

Proceedings of the VLSI: Systems on a Chip, 1999

On Reducing Transitions Through Data Modifications.

[BibT_eX]

[DOI]

Proceedings of the 1999 Design, 1999

Multiple Error Diagnosis Based on Xlists.

[BibT_eX]

[DOI]

Proceedings of the 36th Conference on Design Automation, 1999

Symbolic Model Checking Using SAT Procedures instead of BDDs.

[BibT_eX]

[DOI]

Proceedings of the 36th Conference on Design Automation, 1999

Development of an optimizing compiler for a Fujitsu fixed-point digital signal processor.

[BibT_eX]

[DOI]

Proceedings of the Seventh International Workshop on Hardware/Software Codesign, 1999

Program Slicing of Hardware Description Languages.

[BibT_eX]

[DOI]

Proceedings of the Correct Hardware Design and Verification Methods, 1999

Model Checking Based on Sequential ATPG.

[BibT_eX]

[DOI]

Proceedings of the Computer Aided Verification, 11th International Conference, 1999

1998

ATM switch design by high-level modeling, formal verification and high-level synthesis.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 1998

Development of an Autonomous Quadruped Robot for Robot Entertainment.

[BibT_eX]

[DOI]

Auton. Robots, 1998

Integration of High-Level Modeling, Formal Verification, and High-Level Synthesis in ATM Switch Design.

[BibT_eX]

[DOI]

Sreeranga P. Rajan

Proceedings of the 11th International Conference on VLSI Design (VLSI Design 1991), 1998

A Quadruped Robot for RoboCup Legged Robot Challenge in Paris '98.

[BibT_eX]

[DOI]

Stéphane Zrehen

Proceedings of the RoboCup-98: Robot Soccer World Cup II, 1998

Modeling the unknown! Towards model-independent fault and error diagnosis.

[BibT_eX]

[DOI]

Vamsi Boppana

Proceedings of the Proceedings IEEE International Test Conference 1998, 1998

Playing soccer with legged robots.

[BibT_eX]

[DOI]

Proceedings of the Proceedings 1998 IEEE/RSJ International Conference on Intelligent Robots and Systems. Innovations in Theory, 1998

Sony Legged Robot for RoboCup Challenge.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference on Robotics and Automation, 1998

Sampling schemes for computing OBDD variable orderings.

[BibT_eX]

[DOI]

William Adams

Proceedings of the 1998 IEEE/ACM International Conference on Computer-Aided Design, 1998

Two Real Formal Verification Experiences: ATM Switch Chip and Parallel Cache Protocol.

[BibT_eX]

[DOI]

Sreeranga P. Rajan

Alan J. Hu

Proceedings of the Applied Formal Methods, 1998

Using Complementation and Resequencing to Minimize Transitions.

[BibT_eX]

[DOI]

Arlindo L. Oliveira

Proceedings of the 35th Conference on Design Automation, 1998

Model Checking: Its Basics and Reality (Embedded Tutorial).

[BibT_eX]

[DOI]

Proceedings of the ASP-DAC '98, 1998

An Open Architecture of Remotion and Behavior Control of Autonomous Agents.

[BibT_eX]

[DOI]

Juan David Velásquez

Proceedings of the Second International Conference on Autonomous Agents, 1998

Reconfigurable Physical Agents.

[BibT_eX]

[DOI]

Proceedings of the Second International Conference on Autonomous Agents, 1998

1997

Power analysis and minimization techniques for embedded DSP software.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 1997

Multi-Terminal Binary Decision Diagrams: An Efficient Data Structure for Matrix Representation.

[BibT_eX]

[DOI]

Patrick C. McGeer

Jerry Chih-Yuan Yang

Formal Methods Syst. Des., 1997

Introduction to the Special Issue on Multi-Terminal Binary Decision Diagrams.

[BibT_eX]

[DOI]

Patrick C. McGeer

Formal Methods Syst. Des., 1997

Spectral Transforms for Large Boolean Functions with Applications to Technology Mapping.

[BibT_eX]

[DOI]

Formal Methods Syst. Des., 1997

Domain-Specific High-Level Modeling and Synthesis for ATM Switch Prototyping.

[BibT_eX]

[DOI]

Des. Autom. Embed. Syst., 1997

Some Recent Advances in Software and Hardware Logic Simulation.

[BibT_eX]

[DOI]

Proceedings of the 10th International Conference on VLSI Design (VLSI Design 1997), 1997

Formal Verification of Combinational Circuit.

[BibT_eX]

[DOI]

Amit Narayan

Proceedings of the 10th International Conference on VLSI Design (VLSI Design 1997), 1997

A Legged Robot for RoboCup Based on "OPENR".

[BibT_eX]

[DOI]

Proceedings of the RoboCup-97: Robot Soccer World Cup I, 1997

A proposal of a quadruped robot platform for RoboCup.

[BibT_eX]

[DOI]

Proceedings of the 1997 IEEE/RSJ International Conference on Intelligent Robot and Systems. Innovative Robotics for Real-World Applications. IROS '97, 1997

A Survey of Techniques for Formal Verification of Combinational Circuits.

[BibT_eX]

[DOI]

Amit Narayan

Proceedings of the Proceedings 1997 International Conference on Computer Design: VLSI in Computers & Processors, 1997

Formal Verification of the HAL S1 System Cache Coherence Protocol.

[BibT_eX]

[DOI]

Alan J. Hu

Chris Wilson

Proceedings of the Proceedings 1997 International Conference on Computer Design: VLSI in Computers & Processors, 1997

Speeding up technology-independent timing optimization by network partitioning.

[BibT_eX]

[DOI]

Rajat Aggarwal

Proceedings of the 1997 IEEE/ACM International Conference on Computer-Aided Design, 1997

ATM Switch Design: Parametric High-Level Modeling and Formal Verification.

[BibT_eX]

[DOI]

Sreeranga P. Rajan

Proceedings of the Algebraic Methodology and Software Technology, 1997

An Open Architecture for Robot Entertainment.

[BibT_eX]

[DOI]

Proceedings of the First International Conference on Autonomous Agents, 1997

1996

Solving the net matching problem in high-performance chip design.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1996

Hybrid Position and Force Control Without Force Sensor.

[BibT_eX]

[DOI]

Kiyoshi Ohishi

Masaru Miyazaki

J. Robotics Mechatronics, 1996

A study of composition schemes for mixed apply/compose based construction of ROBDDs.

[BibT_eX]

[DOI]

Proceedings of the 9th International Conference on VLSI Design (VLSI Design 1996), 1996

On More Efficient Combinational ATPG Using Functional Learning.

[BibT_eX]

[DOI]

Proceedings of the 9th International Conference on VLSI Design (VLSI Design 1996), 1996

Partitioned ROBDDs - a compact, canonical and efficiently manipulable representation for Boolean functions.

[BibT_eX]

[DOI]

Amit Narayan

Proceedings of the 1996 IEEE/ACM International Conference on Computer-Aided Design, 1996

Decomposition Techniques for Efficient ROBDD Construction.

[BibT_eX]

[DOI]

Robert K. Brayton

Proceedings of the Formal Methods in Computer-Aided Design, First International Conference, 1996

Domain-Specific High-Level Modeling and Synthesis for ATM Switch Design Using VHDL.

[BibT_eX]

[DOI]

Proceedings of the 33st Conference on Design Automation, 1996

Verification of Arithmetic Circuits by Comparing Two Similar Circuits.

[BibT_eX]

[DOI]

Proceedings of the Computer Aided Verification, 8th International Conference, 1996

1995

Power analysis and low-power scheduling techniques for embedded DSP software.

[BibT_eX]

[DOI]

Proceedings of the 8th International Symposium on System Synthesis (ISSS 1995), 1995

Logic synthesis for a single large look-up table.

[BibT_eX]

[DOI]

Fumiyasu Hirose

Proceedings of the 1995 International Conference on Computer Design (ICCD '95), 1995

Simple tree-construction heuristics for the fanout problem .

[BibT_eX]

[DOI]

Robert J. Carragher

Chung-Kuan Cheng

Proceedings of the 1995 International Conference on Computer Design (ICCD '95), 1995

Hybrid decision diagrams.

[BibT_eX]

[DOI]

Edmund M. Clarke

Xudong Zhao

Proceedings of the 1995 IEEE/ACM International Conference on Computer-Aided Design, 1995

VERIFUL: VERIfication using FUnctional Learning.

[BibT_eX]

[DOI]

Rajarshi Mukherjee

Proceedings of the 1995 European Design and Test Conference, 1995

Advanced Verification Techniques Based on Learning.

[BibT_eX]

[DOI]

Rajarshi Mukherjee

Proceedings of the 32st Conference on Design Automation, 1995

1994

Fast Spectrum Computation for Logic Functions using Binary Decision Diagrams.

[BibT_eX]

[DOI]

Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994

YEPHCAD and FLORA: Logic Synthesis for Control and Datapath.

[BibT_eX]

[DOI]

Hitomi Sato

Michihiro Yamazaki

Proceedings of the Proceedings 1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1994

LP based cell selection with constraints of timing, area, and power consumption.

[BibT_eX]

[DOI]

Yutaka Tamiya

Proceedings of the 1994 IEEE/ACM International Conference on Computer-Aided Design, 1994

A redesign technique for combinational circuits based on gate reconnections.

[BibT_eX]

[DOI]

Yuji Kukimoto

Robert K. Brayton

Proceedings of the 1994 IEEE/ACM International Conference on Computer-Aided Design, 1994

Bug Identification of a Real Chip Design by Symbolic Model Checking.

[BibT_eX]

[DOI]

Ben Chen

Michihiro Yamazaki

Proceedings of the EDAC - The European Conference on Design Automation, ETC - European Test Conference, EUROASIC - The European Event in ASIC Design, Proceedings, February 28, 1994

1993

Variable ordering algorithms for ordered binary decision diagrams and their evaluation.

[BibT_eX]

[DOI]

Hisanori Fujisawa

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1993

Motion Planning and Control for a Robot Performer.

[BibT_eX]

[DOI]

Proceedings of the 1993 IEEE International Conference on Robotics and Automation, 1993

Synthesis of Controllers from Interval Temporal Logic Specification.

[BibT_eX]

[DOI]

Shinji Kono

Proceedings of the Proceedings 1993 International Conference on Computer Design: VLSI in Computers & Processors, 1993

An efficient algorithm for the net matching problem.

[BibT_eX]

[DOI]

Robert J. Carragher

Chung-Kuan Cheng

Proceedings of the 1993 IEEE/ACM International Conference on Computer-Aided Design, 1993

1992

Force control without force sensor based on mixed sensitivity H ∞ design method.

[BibT_eX]

[DOI]

Proceedings of the 1992 IEEE International Conference on Robotics and Automation, 1992

RTL Design Verification by Making Use of Datapath Information.

[BibT_eX]

[DOI]

Proceedings of the Proceedings 1992 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1992

Rectification method for lookup-table type FPGA's.

[BibT_eX]

[DOI]

Yuji Kukimoto

Proceedings of the 1992 IEEE/ACM International Conference on Computer-Aided Design, 1992

Patching Method for Lookup-Table Type FPLs.

[BibT_eX]

[DOI]

Yuji Kukimoto

Proceedings of the Field-Programmable Gate Arrays: Architectures and Tools for Rapid Prototyping, Second International Workshop on Field-Programmable Logic and Applications, Vienna, Austria, August 31, 1992

Efficient Sum-to-One Subsets Algorithm for Logic Optimization.

[BibT_eX]

[DOI]

Kuang-Chien Chen

Proceedings of the 29th Design Automation Conference, 1992

1991

Analysis of Neighborhood Interaction in Kohonen Neural Networks.

[BibT_eX]

[DOI]

Zhen-Ping Lo

Behnam Bavarian

Proceedings of the Fifth International Parallel Processing Symposium, Proceedings, Anaheim, California, USA, April 30, 1991

Concurrent Resynthesis for Network Optimization.

[BibT_eX]

[DOI]

Kuang-Chien Chen

Proceedings of the Proceedings 1991 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1991

Application of Boolean Unification to Combinational Logic Synthesis.

[BibT_eX]

[DOI]

Proceedings of the 1991 IEEE/ACM International Conference on Computer-Aided Design, 1991

Multi-Level Logic Minimization Based on Minimal Support and its Application to the Minimization of Look-Up Table Type FPGAs.

[BibT_eX]

[DOI]

Proceedings of the 1991 IEEE/ACM International Conference on Computer-Aided Design, 1991

On variable ordering of binary decision diagrams for the application of multi-level logic synthesis.

[BibT_eX]

[DOI]

Taeko Kakuda

Proceedings of the conference on European design automation, 1991

A Resynthesis Approach for Network Optimization.

[BibT_eX]

[DOI]

Proceedings of the 28th Design Automation Conference, 1991

1990

Speed tunable finite state machine compiler: Zephcad.

[BibT_eX]

[DOI]

Hitomi Sato

Yoshihide Sugiura

Microprocess. Microsystems, 1990

Boolean technology mapping for both ECI and CMOS circuits based on permissible functions and binary decision diagrams.

[BibT_eX]

[DOI]

Proceedings of the 1990 IEEE International Conference on Computer Design: VLSI in Computers and Processors, 1990

Practical design assistance at register transfer level using a data path verifier.

[BibT_eX]

[DOI]

Proceedings of the 1990 IEEE International Conference on Computer Design: VLSI in Computers and Processors, 1990

Multi-Level Logic Minimization Across Latch Boundaries.

[BibT_eX]

[DOI]

Takeo Kakuda

Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 1990

Automatic and Semi-Automatic Verification of Switch-Level Circuits with Temporal Logic and Binary Decision Diagrams.

[BibT_eX]

[DOI]

Takeo Kakuda

Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 1990

Boolean Resubstitution with Permissible Functions and Binary Decision Diagrams.

[BibT_eX]

[DOI]

Proceedings of the 27th ACM/IEEE Design Automation Conference. Orlando, 1990

A Data Path Verifier for Register Transfer Level Using Temporal Logic Language Tokio.

[BibT_eX]

[DOI]

Proceedings of the Computer Aided Verification, 2nd International Workshop, 1990

Implementation of ANN on RISC processor array.

[BibT_eX]

[DOI]

Proceedings of the Application Specific Array Processors, 1990

1989

Logic Design Assistence Using Temporal Logic Based Language Tokio.

[BibT_eX]

[DOI]

Proceedings of the Logic Programming '89, 1989

Multi-level logic optimization using binary decision diagrams.

[BibT_eX]

[DOI]

Proceedings of the 1989 IEEE International Conference on Computer-Aided Design, 1989

1988

Evaluation and improvement of Boolean comparison method based on binary decision diagrams.

[BibT_eX]

[DOI]

Hisanori Fujisawa

Nobuaki Kawato

Proceedings of the 1988 IEEE International Conference on Computer-Aided Design, 1988

1986

Tokio: Logic Programming Language Based on Temporal Logic and its Compilation to Prolog.

[BibT_eX]

[DOI]

Proceedings of the Third International Conference on Logic Programming, 1986

1985

Implementation of Temporal Logic Programming Language Tokio.

[BibT_eX]

[DOI]

Proceedings of the Logic Programming '85, 1985

Using the Temporal Logic Programming Language Tokio for Algorithm Description and Automatic CMOS Gate Array Synthesis.

[BibT_eX]

[DOI]

Proceedings of the Logic Programming '85, 1985

Temporal Logic Programming Language Tokio - Programming in Tokio.

[BibT_eX]

[DOI]

T. Aoyagi

Tohru Moto-Oka

Proceedings of the Logic Programming '85, 1985

1984

Specifying Hardware in temporal Logic & Efficient Synthesis of State-Diagrams Using Prolog.

[BibT_eX]

Hidehiko Tanaka

Tohru Moto-Oka

Proceedings of the International Conference on Fifth Generation Computer Systems, 1984

1983

Temporal Logic Based Hardware Description and Its Verification with Prolog.

[BibT_eX]

[DOI]