Masahiko Nishiyama

According to our database, Masahiko Nishiyama authored at least 3 papers between 1996 and 2000.

Collaborative distances:

• Dijkstra number of six.
• Erdős number of five.

2000

Power reduction techniques for a 1-Mb ECL-CMOS SRAM with an access time of 550 ps and an operating frequency of 900 MHz.

Kenichi Ohhata, Fumihiko Arakawa, Takeshi Kusunoki, Hiroaki Nambu, Kazuo Kanetani, Kaname Yamasaki, Keiichi Higeta, Masami Usami, Masahiko Nishiyama, Kunihiko Yamaguchi, Noriyuki Homma, Atsuo Hotta

IEEE J. Solid State Circuits, 2000

A 550-ps access 900-MHz 1-Mb ECL-CMOS SRAM.

Hiroaki Nambu, Kazuo Kanetani, Kaname Yamasaki, Keiichi Higeta, Masami Usami, Masahiko Nishiyama, Kenichi Ohhata, Fumihiko Arakawa, Takeshi Kusunoki, Kunihiko Yamaguchi, Atsuo Hotta, Noriyuki Homma

IEEE J. Solid State Circuits, 2000

1996

A soft-error-immune 0.9-ns 1.15-Mb ECL-CMOS SRAM with 30-ps 120 k logic gates and on-chip test circuitry.

Keiichi Higeta, Masami Usami, Masayuki Ohayashi, Yasuhiro Fujimura, Masahiko Nishiyama, Satoru Isomura, Kunihiko Yamaguchi, Youji Idei, Hiroaki Nambu, Kenichi Ohhata, Nadateru Hanta

IEEE J. Solid State Circuits, 1996