Masahide Takada

According to our database1, Masahide Takada authored at least 13 papers between 1988 and 1996.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

1988
1989
1990
1991
1992
1993
1994
1995
1996
0
1
2
3
4
3
1
1
2
2
2
1
1

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

1996
A 6-ns, 1.5-V, 4-Mb BiCMOS SRAM.
IEEE J. Solid State Circuits, 1996

A sub-2.0 V BiCMOS logic circuit with a BiCMOS charge pump.
IEEE J. Solid State Circuits, 1996

A 60-ns 1-Mb nonvolatile ferroelectric memory with a nondriven cell plate line write/read scheme.
IEEE J. Solid State Circuits, 1996

1995
A 1 ns, 1 W, 2.5 V, 32 Kb NTL-CMOS SRAM macro using a memory cell with PMOS access transistors.
IEEE J. Solid State Circuits, November, 1995

1994
A 220-MHz pipelined 16-Mb BiCMOS SRAM with PLL proportional self-timing generator.
IEEE J. Solid State Circuits, November, 1994

1993
A 300-MHz 16-b BiCMOS video signal processor.
IEEE J. Solid State Circuits, December, 1993

Memory LSI reliability.
Proc. IEEE, 1993

1992
A 30-ns 64-Mb DRAM with built-in self-test and self-repair function.
IEEE J. Solid State Circuits, November, 1992

A 6-ns ECL 100 K I/O and 8-ns 3.3-V TTL I/O 4-Mb BiCMOS SRAM.
IEEE J. Solid State Circuits, November, 1992

1990
A 5-ns 1-Mb ECL BiCMOS SRAM.
IEEE J. Solid State Circuits, October, 1990

A 55-ns 16-Mb DRAM with built-in self-test function using microprogram ROM.
IEEE J. Solid State Circuits, August, 1990

A BIST scheme using microprogram ROM for large capacity memories.
Proceedings of the Proceedings IEEE International Test Conference 1990, 1990

1988
Voltage limiters for DRAMs with substrate-plate-electrode memory cells.
IEEE J. Solid State Circuits, February, 1988


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