Masaharu Terada

According to our database1, Masaharu Terada authored at least 6 papers between 2011 and 2013.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2013
A 40-nm 0.5-V 12.9-pJ/Access 8T SRAM using low-power disturb mitigation technique.
Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013

2012
A 40-nm 0.5-V 12.9-pJ/Access 8T SRAM Using Low-Energy Disturb Mitigation Scheme.
IEICE Trans. Electron., 2012

A 40-nm 256-Kb Half-Select Resilient 8T SRAM with Sequential Writing Technique.
IEICE Electron. Express, 2012

A 40-nm 256-Kb 0.6-V operation half-select resilient 8T SRAM with sequential writing technique enabling 367-mV VDDmin reduction.
Proceedings of the Thirteenth International Symposium on Quality Electronic Design, 2012

A 40-nm 256-Kb Sub-10 pJ/Access 8t SRAM with read bitline amplitude limiting (RBAL) scheme.
Proceedings of the International Symposium on Low Power Electronics and Design, 2012

2011
Information and communication technology infrastructure and management for collaboration with regional universities and colleges.
Proceedings of the ACM SIGUCCS Fall Conference on User Services 2011, 2011


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