Masaharu Imai

According to our database, Masaharu Imai authored at least 84 papers between 1979 and 2023.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2023

EMoDi: Entity-Enhanced Momentum-Difference Contrastive Learning for Semantic-Aware Verification of Scientific Information.

Ze Yang, Yimeng Sun, Takao Nakaguchi, Masaharu Imai

Proceedings of the IEEE International Conference on Knowledge Graph, 2023

2018

Decomposed Vector Histograms of Oriented Gradients for Efficient Hardware Implementation.

Koichi Mitsunari, Yoshinori Takeuchi, Masaharu Imai, Jaehoon Yu

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2018

2017

A Low-Energy Application Specific Instruction-Set Processor towards a Low-Computational Lossless Compression Method for Stimuli Position Data of Artificial Vision Systems.

Tomoki Sugiura, Masaharu Imai, Jaehoon Yu, Yoshinori Takeuchi

J. Inf. Process., 2017

Deformable Part Model Based Arrhythmia Detection Using Time Domain Features.

Yuuka Hirao, Yoshinori Takeuchi, Masaharu Imai, Jaehoon Yu

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2017

Flexible sensor sheet for real-time pressure monitoring in artificial knee joint during total knee arthroplasty.

Fumika Tanabe, Shusuke Yoshimoto, Yuki Noda, Teppei Araki, Takafumi Uemura, Yoshinori Takeuchi, Masaharu Imai, Tsuyoshi Sekitani

Proceedings of the 2017 39th Annual International Conference of the IEEE Engineering in Medicine and Biology Society (EMBC), 2017

Emerging technologies for biomedical applications: Artificial vision systems and brain machine interface.

Masaharu Imai, Yoshinori Takeuchi, Jun Ohta, Gregg Jørgen Suaning, Chung-Yu Wu, Napoleon Torres-Martinez

Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017

2016

A programmable controller for spatio-temporal pattern stimulation of cortical visual prosthesis.

Tomoki Sugiura, Arif Ullah Khan, Jaehoon Yu, Yoshinori Takeuchi, Seiji Kameda, Takatsugu Kamata, Yuki Hayashida, Tetsuya Yagi, Masaharu Imai

Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2016

2015

An Efficient Performance Estimation Method for Configurable Multi-layer Bus-based SoC.

Salita Sombatsiri, Yoshinori Takeuchi, Masaharu Imai

IPSJ Trans. Syst. LSI Des. Methodol., 2015

Preliminary study of a new home healthcare monitoring to prevent the recurrence of stroke.

Toshiyo Tamura, Masaki Sekine, Zunyi Tang, Masaki Yoshida, Yoshinori Takeuchi, Masaharu Imai

Proceedings of the 37th Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2015

Cortical neural excitations in rats in vivo with using a prototype of a wireless multi-channel microstimulation system.

Yuki Hayashida, Yuichi Umehira, Kouki Takatani, Shigetoshi Futami, Seiji Kameda, Takatsugu Kamata, Arif Ullah Khan, Yoshinori Takeuchi, Masaharu Imai, Tetsuya Yagi

Proceedings of the 37th Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2015

A low-energy ASIP with flexible exponential Golomb codec for lossless data compression toward artificial vision systems.

Tomoki Sugiura, Jaehoon Yu, Yoshinori Takeuchi, Masaharu Imai

Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2015

2014

A New Available Bandwidth Estimation Method Using RTT for a Bottleneck Link.

Masaharu Imai, Yoshio Sugizaki, Koichi Asatani

IEICE Trans. Commun., 2014

An efficient data compression method for artificial vision systems and its low energy implementation using ASIP technology.

Tomoki Sugiura, Shoko Nakatsuka, Jaehoon Yu, Yoshinori Takeuchi, Masaharu Imai

Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2014

2013

Electronic triage system for continuously monitoring casualties at disaster scenes.

Keishi Sakanushi, Takuji Hieda, Taichiro Shiraishi, Yasumasa Ode, Yoshinori Takeuchi, Masaharu Imai, Teruo Higashino, Hiroshi Tanaka

J. Ambient Intell. Humaniz. Comput., 2013

A new estimation method using RTT for available bandwidth of a bottleneck link.

Masaharu Imai, Yoshio Sugizaki, Koichi Asatani

Proceedings of the International Conference on Information Networking 2013, 2013

An efficient lossless data compression method based on exponential-Golomb coding for biomedical information and its implementation using ASIP technology.

Shoko Nakatsuka, Takashi Hamabe, Yoshinori Takeuchi, Masaharu Imai

Proceedings of the 2013 IEEE Biomedical Circuits and Systems Conference (BioCAS), Rotterdam, The Netherlands, October 31, 2013

Error analysis of an estimation method using RTT for available bandwidth of a bottleneck link.

Masaharu Imai, Takayuki Ozawa, Yoshio Sugizaki, Koichi Asatani

Proceedings of the 15th Asia-Pacific Network Operations and Management Symposium, 2013

2012

A Small-Area and Low-Power SoC for Less-Invasive Pressure Sensing Capsules in Ambulatory Urodynamic Monitoring.

Hirofumi Iwato, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai

IEICE Trans. Electron., 2012

On-chip Communication Buffer Architecture Optimization Considering Bus Width.

Salita Sombatsiri, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai

Proceedings of the IEEE 6th International Symposium on Embedded Multicore/Manycore SoCs, 2012

Task Allocation and Scheduling for Voltage-Frequency Islands Applied NoC-based MPSoC Considering Network Congestion.

Sho Ninomiya, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai

Proceedings of the IEEE 6th International Symposium on Embedded Multicore/Manycore SoCs, 2012

2011

Two-Stage Configurable Decoder Model for Domain Specific FEC Decoder Design.

Ittetsu Taniguchi, Ayataka Kobayashi, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2011

Automated architecture exploration for low energy reconfigurable AGU.

Ittetsu Taniguchi, Murali Jayapala, Praveen Raghavan, Francky Catthoor, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai

Proceedings of the International SoC Design Conference, 2011

Biological information sensing technologies for medical, health care, and wellness applications.

Masaharu Imai, Yoshinori Takeuchi, Keishi Sakanushi, Hirofumi Iwato

Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011

Electronic Triage System: Casualties Monitoring System in the Disaster Scene.

Keishi Sakanushi, Takuji Hieda, Taichiro Shiraishi, Yasumasa Ode, Yoshinori Takeuchi, Masaharu Imai, Teruo Higashino, Hiroshi Tanaka

Proceedings of the 2011 International Conference on P2P, 2011

2010

Software Development Tool Generation Method Suitable for Instruction Set Extension of Embedded Processors.

Takahiro Kumura, Soichiro Taga, Nagisa Ishiura, Yoshinori Takeuchi, Masaharu Imai

IPSJ Trans. Syst. LSI Des. Methodol., 2010

A Low-power ASIP Generation Method by Extracting Minimum Execution Conditions.

Hirofumi Iwato, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai

IPSJ Trans. Syst. LSI Des. Methodol., 2010

Advantage and Possibility of Application-domain Specific Instruction-set Processor (ASIP).

Masaharu Imai, Yoshinori Takeuchi, Keishi Sakanushi, Nagisa Ishiura

IPSJ Trans. Syst. LSI Des. Methodol., 2010

Efficient partitioning technique on multiple cores based on optimal scheduling and mapping algorithm.

Hassan A. Youness, Abdel-Moniem Wahdan, Mohammed Hassan, Ashraf Salem, Mohammed Moness, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

Two-stage configurable decoder model for multiple forward error correction standards.

Ittetsu Taniguchi, Ayataka Kobayashi, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai

Proceedings of the 8th IEEE Workshop on Embedded Systems for Real-Time Multimedia, 2010

A new compilation technique for SIMD code generation across basic block boundaries.

Hiroaki Tanaka, Yutaka Ota, Nobu Matsumoto, Takuji Hieda, Yoshinori Takeuchi, Masaharu Imai

Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010

2009

Optimal Scheme for Search State Space and Scheduling on Multiprocessor Systems.

Hassan A. Youness, Keishi Sakanushi, Yoshinori Takeuchi, Ashraf Salem, Abdel-Moniem Wahdan, Masaharu Imai

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009

Reconfigurable AGU: An Address Generation Unit Based on Address Calculation Pattern for Low Energy and High Performance Embedded Processors.

Ittetsu Taniguchi, Praveen Raghavan, Murali Jayapala, Francky Catthoor, Yoshinori Takeuchi, Masaharu Imai

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009

Heuristic Instruction Scheduling Algorithm Using Available Distance for Partial Forwarding Processor.

Takuji Hieda, Hiroaki Tanaka, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009

Systematic architecture exploration based on optimistic cycle estimation for low energy embedded processors.

Ittetsu Taniguchi, Murali Jayapala, Praveen Raghavan, Francky Catthoor, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai

Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009

2008

Efficient Method to Generate an Energy Efficient Schedule Using Operation Shuffling.

Yuki Kobayashi, Murali Jayapala, Praveen Raghavan, Francky Catthoor, Masaharu Imai

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008

Operation shuffling over cycle boundaries for low energy L0 clustering.

Yuki Kobayashi, Murali Jayapala, Praveen Raghavan, Francky Catthoor, Masaharu Imai

Proceedings of the 19th IEEE International Conference on Application-Specific Systems, 2008

2007

Methodology for operation shuffling and L0 cluster generation for low energy heterogeneous VLIW processors.

Yuki Kobayashi, Murali Jayapala, Praveen Raghavan, Francky Catthoor, Masaharu Imai

ACM Trans. Design Autom. Electr. Syst., 2007

Generation of Pack Instruction Sequence for Media Processors Using Multi-Valued Decision Diagram.

Hiroaki Tanaka, Yoshinori Takeuchi, Keishi Sakanushi, Masaharu Imai, Hiroki Tagawa, Yutaka Ota, Nobu Matsumoto

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2007

A Block-Floating-Point Processor for Rapid Application Development.

Hiroaki Tanaka, Yoshinori Takeuchi, Keishi Sakanushi, Masaharu Imai, Shiro Kobayashi

Proceedings of the IEEE International Conference on Acoustics, 2007

A low power VLIW processor generation method by means of extracting non-redundant activation conditions.

Hirofumi Iwato, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai

Proceedings of the 5th International Conference on Hardware/Software Codesign and System Synthesis, 2007

A Processor Generation Method from Instruction Behavior Description Based on Specification of Pipeline Stages and Functional Units.

Takeshi Shiro, Masaaki Abe, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai

Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007

2006

Task Partitioning Oriented Architecture Exploration Method for Dynamic Reconfigurable Architectures.

Ittetsu Taniguchi, Kyoko Ueda, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai

Proceedings of the IFIP VLSI-SoC 2006, 2006

Dynamic Reconfigurable Architecture Exploration based on Parameterized Reconfigurable Processor Model.

Ittetsu Taniguchi, Keishi Sakanushi, Kyoko Ueda, Yoshinori Takeuchi, Masaharu Imai

Proceedings of the VLSI-SoC: Research Trends in VLSI and Systems on Chip, 2006

Pack instruction generation for media pUsing multi-valued decision diagram.

Hiroaki Tanaka, Yoshinori Takeuchi, Keishi Sakanushi, Masaharu Imai, Yutaka Ota, Nobu Matsumoto, Masaki Nakagawa

Proceedings of the 4th International Conference on Hardware/Software Codesign and System Synthesis, 2006

2005

Operation Shuffling for Low Energy L0 Cluster Generation on Heterogeneous VLIW Processors.

Yuki Kobayashi, Murali Jayapala, Praveen Raghavan, Francky Catthoor, Masaharu Imai

Proceedings of the 2005 3rd Workshop on Embedded Systems for Real-Time Multimedia, 2005

RTK-Spec TRON: A Simulation Model of an ITRON Based RTOS Kernel in SystemC.

M. Abdelsalam Hassan, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai

Proceedings of the 2005 Design, 2005

Verification Challenges in Configurable Processor Design with ASIP Meister.

Masaharu Imai, Akira Kitajima

Proceedings of the Correct Hardware Design and Verification Methods, 2005

Enabling RTOS simulation modeling in a system level design language.

M. Abdelsalam Hassan, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai

Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

2004

S-sequence: a new floorplan representation method preserving room abutment relationships.

Yohei Ishimaru, Keishi Sakanushi, Shinsuke Kobayashi, Yoshinori Takeuchi, Masaharu Imai

Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

Towards a Higher Level of Abstraction in Hardware/Software Co-Simulation.

H. M. AbdElSalam, Shinsuke Kobayashi, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai

Proceedings of the 24th International Conference on Distributed Computing Systems Workshops (ICDCS 2004 Workshops), 2004

Architecture-Level Performance Estimation for IP-Based Embedded Systems.

Kyoko Ueda, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai

Proceedings of the 2004 Design, 2004

Synthesizable HDL generation method for configurable VLIW processors.

Yuki Kobayashi, Shinsuke Kobayashi, Koji Okuda, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai

Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004

2003

Foreword.

Masaharu Imai

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2003

A Code Selection Method for SIMD Processors with PACK Instructions.

Hiroaki Tanaka, Shinsuke Kobayashi, Yoshinori Takeuchi, Keishi Sakanushi, Masaharu Imai

Proceedings of the Software and Compilers for Embedded Systems, 7th International Workshop, 2003

Rapid prototyping of JPEG encoder using the ASIP development system: PEAS-III.

Shinsuke Kobayashi, Kentaro Mita, Yoshinori Takeuchi, Masaharu Imai

Proceedings of the 2003 IEEE International Conference on Acoustics, 2003

2002

A Compiler Generation Method for HW/SW Codesign Based on Configurable Processors.

Shinsuke Kobayashi, Kentaro Mita, Yoshinori Takeuchi, Masaharu Imai

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2002

Design of Application Specific CISC Using PEAS-III.

Akira Kitajima, Toshiyuki Sasaki, Yoshinori Takeuchi, Masaharu Imai

Proceedings of the 13th IEEE International Workshop on Rapid System Prototyping (RSP 2002), 2002

Design space exploration for DSP applications using the ASIP development system PEAS-III.

Shinsuke Kobayashi, Kentaro Mita, Yoshinori Takeuchi, Masaharu Imai

Proceedings of the IEEE International Conference on Acoustics, 2002

2001

VLSI Implementation of Fractal Image Compression Processor for Moving Pictures.

Hideki Yamauchi, Yoshinori Takeuchi, Masaharu Imai

Proceedings of the 27th EUROMICRO Conference 2001: A Net Odyssey, 2001

Effectiveness of the ASIP design system PEAS-III in design of pipelined processors.

Akira Kitajima, Makiko Itoh, Jun Sato, Akichika Shiomi, Yoshinori Takeuchi, Masaharu Imai

Proceedings of ASP-DAC 2001, 2001

2000

PEAS-III: An ASIP Design Environment.

Makiko Itoh, Shigeaki Higaki, Yoshinori Takeuchi, Akira Kitajima, Masaharu Imai, Jun Sato, Akichika Shiomi

Proceedings of the IEEE International Conference On Computer Design: VLSI In Computers & Processors, 2000

One language or more?: how can we design an SoC at a system level?

Masaharu Imai, Gary Smith, Steven Schulz, Karen Bartleson, Daniel Gajski, Wolfgang Rosenstiel, Peter Flake, Hiroto Yasuura

Proceedings of ASP-DAC 2000, 2000

1999

A programmable processor with multiple functional units and banked registers for general purpose numerical processing.

Takafumi Morifuji, Yoshinori Takeuchi, Masaharu Imai

Proceedings of the 1999 IEEE International Conference on Acoustics, 1999

Application of FHM-Based Design Method to Scalable 2-D DCT Processor.

Eiichirou Shigehara, Yoshinori Takeuchi, Masaharu Imai, Tsutomu Kimura

Proceedings of the 25th EUROMICRO '99 Conference, 1999

1998

A Performance Maximization Algorithm to Design ASIPs under the Constraint of Chip Area Including RAM and ROM Sizes.

Nguyen-Ngoc Bình, Masaharu Imai, Yoshinori Takeuchi

Proceedings of the ASP-DAC '98, 1998

1997

VLSI implementation of a real-time operating system.

Takumi Nakano, Yoshiki Komatsudaira, Akichika Shiomi, Masaharu Imai

Proceedings of the ASP-DAC '97 Asia and South Pacific Design Automation Conference, 1997

1996

VLSI implementation and evaluation of a real-time operating system.

Takumi Nakano, Andy Utama, Akichika Shiomi, Masaharu Imai, Mitsuyoshi Itabashi

Syst. Comput. Jpn., 1996

ASPDAC 1995: HDL synthesizability and interoperability.

Masaharu Imai, Eugenio Villar

IEEE Des. Test Comput., 1996

A new HW/SW partitioning algorithm for synthesizing the highest performance pipelined ASIPs with multiple identical FUs.

Masaharu Imai, Nguyen-Ngoc Bình, Akichika Shiomi

Proceedings of the conference on European design automation, 1996

A Hardware/Software Partitioning Algorithm for Designing Pipelined ASIPs with Least Gate Counts.

Nguyen-Ngoc Bình, Masaharu Imai, Akichika Shiomi, Nobuyuki Hikichi

Proceedings of the 33st Conference on Design Automation, 1996

1995

A hardware/software partitioning algorithm for pipelined instruction set processor.

Nguyen-Ngoc Bình, Masaharu Imai, Nobuyuki Hikichi

Proceedings of the Proceedings EURO-DAC'95, 1995

Future direction of synthesizabilty and interoperability of HDL's: part 2.

Eugenio Villar, Masaharu Imai

Proceedings of the 1995 Conference on Asia Pacific Design Automation, Makuhari, Massa, Chiba, Japan, August 29, 1995

Future direction of synthesizability and interoperability of HDL's: part 1.

Masaharu Imai, Eugenio Villar

Proceedings of the 1995 Conference on Asia Pacific Design Automation, Makuhari, Massa, Chiba, Japan, August 29, 1995

A hardware/software codesign method for pipelined instruction set processor using adaptive database.

Nguyen-Ngoc Bình, Masaharu Imai, Akichika Shiomi, Nobuyuki Hikichi

Proceedings of the 1995 Conference on Asia Pacific Design Automation, Makuhari, Massa, Chiba, Japan, August 29, 1995

1993

An ASIP instruction set optimization algorithm with functional module sharing constraint.

Alauddin Alomary, Takeharu Nakata, Yoshimichi Honma, Masaharu Imai, Nobuyuki Hikichi

Proceedings of the 1993 IEEE/ACM International Conference on Computer-Aided Design, 1993

PEAS-I: A hardware/software co-design system for ASIPs.

Alauddin Alomary, Takeharu Nakata, Yoshimichi Honma, Jun Sato, Nobuyuki Hikichi, Masaharu Imai

Proceedings of the European Design Automation Conference 1993, 1993

1992

An integer programming approach to instruction implementation method selection problem.

Masaharu Imai, Jun Sato, Alauddin Alomary, Nobuyuki Hikichi

Proceedings of the conference on European design automation, 1992

1991

An Integrated Design Environment for Application Specific Integrated Processor.

Jun Sato, Masaharu Imai, Tetsuya Hakata, Alauddin Y. Alomary, Nobuyuki Hikichi

Proceedings of the Proceedings 1991 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1991

1988

Computational complexity of the file allocation problem in distributed database systems.

Hiroshi Yamasaki, Tomio Hirata, Masaharu Imai, Toshihide Ibaraki

Syst. Comput. Jpn., 1988

Reconfiguration of a fault-tolerant rectangular systolic array.

Yoshinao Suzuki, Tomio Hirata, Masaharu Imai, Masafumi Yamashita, Toshihide Ibaraki

Syst. Comput. Jpn., 1988

1987

Parallel searches of game trees.

Hiromoto Usui, Masafumi Yamashita, Masaharu Imai, Toshihide Ibaraki

Syst. Comput. Jpn., 1987

1986

Implementation of Parallel Prolog on Tree Machines.

Hajime Miura, Masaharu Imai, Masafumi Yamashita, Toshihide Ibaraki

Proceedings of the Fall Joint Computer Conference, November 2-6, 1986, Dallas, Texas, USA, 1986

1984

The Architecture and Efficiency of DON: A Combinatorial Problem Oriented Multicomputer System.

Masaharu Imai, Yuuji Tateizumi, Yuuji Yoshida, Teruo Fukumura

Proceedings of the 4th International Conference on Distributed Computing Systems, 1984

1979

A Parallel Searching Scheme for Multiprocessor Systems and Its Application to Combinatorial Problems.

Masaharu Imai, Yuuji Yoshida, Teruo Fukumura

Proceedings of the Sixth International Joint Conference on Artificial Intelligence, 1979