Masafumi Onouchi

According to our database1, Masafumi Onouchi authored at least 6 papers between 2006 and 2012.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2012
An on-chip 250 mA 40 nm CMOS digital LDO using dynamic sampling clock frequency scaling with offset-free TDC-based voltage sensor.
Proceedings of the IEEE 25th International SOC Conference, 2012

2011
A 1.39-V input fast-transient-response digital LDO composed of low-voltage MOS transistors in 40-nm CMOS process.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2011

2010
A Low-Power Wide-Range Clock Synchronizer With Predictive-Delay-Adjustment Scheme for Continuous Voltage Scaling in DVFS.
IEEE J. Solid State Circuits, 2010

2009
Green Multicore-SoC Software-Execution Framework with Timely-Power-Gating Scheme.
Proceedings of the ICPP 2009, 2009

2008
Heterogeneous Multi-Core Architecture That Enables 54x AAC-LC Stereo Encoding.
IEEE J. Solid State Circuits, 2008

2006
A system-level power-estimation methodology based on IP-level modeling, power-level adjustment, and power accumulation.
Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006


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