Masafumi Nogawa
According to our database1,
Masafumi Nogawa
authored at least 13 papers
between 1994 and 2017.
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Book In proceedings Article PhD thesis Dataset OtherLinks
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Bibliography
2017
25-Gb/s clock and data recovery IC using latch-load combined with CML buffer circuit for delay generation with 65-nm CMOS.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017
2015
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2015
2014
20.1-mW 8-Gbps UWB-IR millimeter-wave transmitter using an OOK pulse modulator based on CMOS inverters.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014
2013
Small and Low-Cost Dual-Rate Optical Triplexer for OLT Transceivers in 10G/1G Co-existing 10G-EPON Systems.
IEICE Trans. Electron., 2013
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013
2012
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012
2008
A 10-Gb/s Burst-Mode Clock-and-Data Recovery IC with Frequency-Adjusting Dual Gated VCOs.
IEICE Trans. Electron., 2008
A PVT Tolerant STM-16 Clock-and-Data Recovery LSI Using an On-Chip Loop-Gain Variation Compensation Architecture in 0.20-µm CMOS/SOI.
IEICE Trans. Electron., 2008
2006
A 12.5-Gb/s Parallel Phase Detection Clock and Data Recovery Circuit in 0.13-$muhbox m$CMOS.
IEEE J. Solid State Circuits, 2006
Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006
1998
A data-transition look-ahead DFF circuit for statistical reduction in power consumption.
IEEE J. Solid State Circuits, 1998
1994
IEEE J. Solid State Circuits, May, 1994