Masab Ahmad
Orcid: 0000-0001-7786-3558
According to our database1,
Masab Ahmad
authored at least 21 papers
between 2014 and 2022.
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Bibliography
2022
A performance predictor for implementation selection of parallelized static and temporal graph algorithms.
Concurr. Comput. Pract. Exp., 2022
2020
In-Hardware Moving Compute to Data Model to Accelerate Thread Synchronization on Large Multicores.
IEEE Micro, 2020
Proceedings of the PMAM@PPoPP '20: Eleventh International Workshop on Programming Models and Applications for Multicores and Manycores colocated with the 25th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, 2020
Accelerating relax-ordered task-parallel workloads using multi-level dependency checking.
Proceedings of the ICS '20: 2020 International Conference on Supercomputing, 2020
2019
IEEE Trans. Dependable Secur. Comput., 2019
Accelerating Synchronization Using Moving Compute to Data Model at 1, 000-core Multicore Scale.
ACM Trans. Archit. Code Optim., 2019
HeteroMap: A Runtime Performance Predictor for Efficient Processing of Graph Analytics on Heterogeneous Multi-Accelerators.
Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2019
POSTER: Exploiting Multi-Level Task Dependencies to Prune Redundant Work in Relax-Ordered Task-Parallel Algorithms.
Proceedings of the 28th International Conference on Parallel Architectures and Compilation Techniques, 2019
2018
Declarative Resilience: A Holistic Soft-Error Resilient Multicore Architecture that Trades off Program Accuracy for Efficiency.
ACM Trans. Embed. Comput. Syst., 2018
Software-Hardware Managed Last-level Cache Allocation Scheme for Large-Scale NVRAM-Based Multicores Executing Parallel Data Analytics Applications.
Proceedings of the 2018 IEEE International Parallel and Distributed Processing Symposium, 2018
Accelerating Synchronization in Graph Analytics Using Moving Compute to Data Model on Tilera TILE-Gx72.
Proceedings of the 36th IEEE International Conference on Computer Design, 2018
2017
Efficient Situational Scheduling of Graph Workloads on Single-Chip Multicores and GPUs.
IEEE Micro, 2017
Accelerating Graph and Machine Learning Workloads Using a Shared Memory Multicore Architecture with Auxiliary Support for In-hardware Explicit Messaging.
Proceedings of the 2017 IEEE International Parallel and Distributed Processing Symposium, 2017
GraphTuner: An Input Dependence Aware Loop Perforation Scheme for Efficient Execution of Approximated Graph Algorithms.
Proceedings of the 2017 IEEE International Conference on Computer Design, 2017
2016
Proceedings of the 2016 IEEE International Symposium on Workload Characterization, 2016
2015
IACR Cryptol. ePrint Arch., 2015
Exploring the performance implications of memory safety primitives in many-core processors executing multi-threaded workloads.
Proceedings of the Fourth Workshop on Hardware and Architectural Support for Security and Privacy, 2015
CRONO: A Benchmark Suite for Multithreaded Graph Algorithms Executing on Futuristic Multicores.
Proceedings of the 2015 IEEE International Symposium on Workload Characterization, 2015
Efficient parallelization of path planning workload on single-chip shared-memory multicores.
Proceedings of the 2015 IEEE High Performance Extreme Computing Conference, 2015
2014
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014