Masaaki Yamada

According to our database1, Masaaki Yamada authored at least 8 papers between 1988 and 2004.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

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Bibliography

2004
Full-Chip Analysis Method of ESD Protection Network.
Proceedings of the 5th International Symposium on Quality of Electronic Design (ISQED 2004), 2004

2000
EMI-noise analysis under ASIC design environment.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000

Repeater insertion method and its application to a 300MHz 128-bit 2-way superscalar microprocessor.
Proceedings of ASP-DAC 2000, 2000

1998
A DRAM module generator with an expandable cell array scheme.
Proceedings of the IEEE 1998 Custom Integrated Circuits Conference, 1998

1995
Power and area optimization by reorganizing CMOS complex gate circuits.
Proceedings of the 1995 International Symposium on Low Power Design 1995, 1995

1990
FOLM-Planner: A New Floorplanner with a Frame Overlapping Floorplan Model Suitable for SOG (Sea-of-Gates) Type Gate Arrays.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 1990

1989
A new approach to the pin assignment problem.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1989

1988
A New Approach to the Pin Assignment Problem.
Proceedings of the 25th ACM/IEEE Conference on Design Automation, 1988


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