Masaaki Kondo

QULATIS: A Quantum Error Correction Methodology toward Lattice Surgery.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2022

Hash Distributed A* on an FPGA.

[BibT_eX]

[DOI]

Ryuichi Sakamoto

Yuriko Ezaki

Proceedings of the HEART 2022: International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies, Tsukuba, Japan, June 9, 2022

Body Bias Control on a CGRA based on Convex Optimization.

[BibT_eX]

[DOI]

Proceedings of the IEEE Symposium in Low-Power and High-Speed Chips, 2022

2021

Efficient and Precise Profiling, Modeling and Management on Power and Performance for Power Constrained HPC Systems.

[BibT_eX]

[DOI]

IEICE Trans. Electron., 2021

Adaptive Resource Management for HPC Systems (Dagstuhl Seminar 21441).

[BibT_eX]

[DOI]

Dagstuhl Reports, 2021

MLMG: Multi-Local and Multi-Global Model Aggregation for Federated Learning.

[BibT_eX]

[DOI]

Yang Qin

Proceedings of the 19th IEEE International Conference on Pervasive Computing and Communications Workshops and other Affiliated Events, 2021

Density-Based Data Selection and Management for Edge Computing.

[BibT_eX]

[DOI]

Hiroki Oikawa

Proceedings of the 19th IEEE International Conference on Pervasive Computing and Communications, 2021

Local Traffic-Based Energy-Efficient Hybrid Switching for On-Chip Networks.

[BibT_eX]

[DOI]

Yuan He

Jinyu Jiao

Proceedings of the 29th Euromicro International Conference on Parallel, 2021

Multi-objective Reinforcement Learning for Energy Harvesting Wireless Sensor Nodes.

[BibT_eX]

[DOI]

Shaswot Shresthamali

Proceedings of the 14th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2021

Path Planning and Moving Obstacle Avoidance with Neuromorphic Computing.

[BibT_eX]

[DOI]

Motoki Sakurai

Yosuke Ueno

Proceedings of the IEEE International Conference on Intelligence and Safety for Robotics, 2021

A Lightweight Interactive Graph Processing Library for Edge Computing in Smart Society.

[BibT_eX]

[DOI]

Jun Zhou

Proceedings of the Ninth International Symposium on Computing and Networking, 2021

Mitigating Process Variations with Cooperative Tuning for Performance and Power through a Simple DSL.

[BibT_eX]

[DOI]

Proceedings of the Ninth International Symposium on Computing and Networking, 2021

QECOOL: On-Line Quantum Error Correction with a Superconducting Decoder for Surface Code.

[BibT_eX]

[DOI]

Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021

Evaluation of SPEC CPU and SPEC OMP on the A64FX.

[BibT_eX]

[DOI]

Yuetsu Kodama

Mitsuhisa Sato

Proceedings of the IEEE International Conference on Cluster Computing, 2021

2020

A Neural Network-Based On-Device Learning Anomaly Detector for Edge Devices.

[BibT_eX]

[DOI]

Mineto Tsukada

IEEE Trans. Computers, 2020

Fast Semi-Supervised Anomaly Detection of Drivers' Behavior using Online Sequential Extreme Learning Machine.

[BibT_eX]

[DOI]

Proceedings of the 23rd IEEE International Conference on Intelligent Transportation Systems, 2020

A Selective Model Aggregation Approach in Federated Learning for Online Anomaly Detection.

[BibT_eX]

[DOI]

Yang Qin

Proceedings of the 2020 International Conferences on Internet of Things (iThings) and IEEE Green Computing and Communications (GreenCom) and IEEE Cyber, 2020

The Effectiveness of Low-Precision Floating Arithmetic on Numerical Codes: A Case Study on Power Consumption.

[BibT_eX]

[DOI]

Proceedings of the International Conference on High Performance Computing in Asia-Pacific Region, 2020

Energy-Efficient On-Chip Networks through Profiled Hybrid Switching.

[BibT_eX]

[DOI]

Proceedings of the GLSVLSI '20: Great Lakes Symposium on VLSI 2020, 2020

2019

Generation High resolution 3D model from natural language by Generative Adversarial Network.

[BibT_eX]

[DOI]

Kentaro Fukamizu

Ryuichi Sakamoto

CoRR, 2019

A Preliminary Evaluation of Building Block Computing Systems.

[BibT_eX]

[DOI]

Proceedings of the 13th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2019

Power Management of Wireless Sensor Nodes with Coordinated Distributed Reinforcement Learning.

[BibT_eX]

[DOI]

Shaswot Shresthamali

Proceedings of the 37th IEEE International Conference on Computer Design, 2019

An Adaptive Abnormal Behavior Detection using Online Sequential Learning.

[BibT_eX]

[DOI]

Proceedings of the 2019 IEEE International Conference on Computational Science and Engineering, 2019

2018

A new device for fiducial registration of image-guided navigation system for liver RFA.

[BibT_eX]

[DOI]

Int. J. Comput. Assist. Radiol. Surg., 2018

A Power Management Framework with Simple DSL for Automatic Power-Performance Optimization on Power-Constrained HPC Systems.

[BibT_eX]

[DOI]

Proceedings of the Supercomputing Frontiers - 4th Asian Conference, 2018

Analyzing Resource Trade-offs in Hardware Overprovisioned Supercomputers.

[BibT_eX]

[DOI]

Proceedings of the 2018 IEEE International Parallel and Distributed Processing Symposium, 2018

OS-ELM-FPGA: An FPGA-Based Online Sequential Unsupervised Anomaly Detector.

[BibT_eX]

[DOI]

Mineto Tsukada

Proceedings of the Euro-Par 2018: Parallel Processing Workshops, 2018

2017

Adaptive Power Management in Solar Energy Harvesting Sensor Node Using Reinforcement Learning.

[BibT_eX]

[DOI]

Shaswot Shresthamali

ACM Trans. Embed. Comput. Syst., 2017

The Design and Implementation of Scalable Deep Neural Network Accelerator Cores.

[BibT_eX]

[DOI]

Proceedings of the 11th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2017

Scalable deep neural network accelerator cores with cubic integration using through chip interface.

[BibT_eX]

[DOI]

Proceedings of the International SoC Design Conference, 2017

Building block multi-chip systems using inductive coupling through chip interface.

[BibT_eX]

[DOI]

Proceedings of the International SoC Design Conference, 2017

Production Hardware Overprovisioning: Real-World Performance Optimization Using an Extensible Power-Aware Resource Management Framework.

[BibT_eX]

[DOI]

Proceedings of the 2017 IEEE International Parallel and Distributed Processing Symposium, 2017

Cooling-Aware Job Scheduling and Node Allocation for Overprovisioned HPC Systems.

[BibT_eX]

[DOI]

Proceedings of the 2017 IEEE International Parallel and Distributed Processing Symposium, 2017

2016

An Operating System Guided Fine-Grained Power Gating Control Based on Runtime Characteristics of Applications.

[BibT_eX]

[DOI]

IEICE Trans. Electron., 2016

A Runtime Optimization Selection Framework to Realize Energy Efficient Networks-on-Chip.

[BibT_eX]

[DOI]

IEICE Trans. Inf. Syst., 2016

Opportunistic circuit-switching for energy efficient on-chip networks.

[BibT_eX]

[DOI]

Yuan He

Proceedings of the 2016 IFIP/IEEE International Conference on Very Large Scale Integration, 2016

Demand-Aware Power Management for Power-Constrained HPC Systems.

[BibT_eX]

[DOI]

Cao Thang

Yuan He

Proceedings of the IEEE/ACM 16th International Symposium on Cluster, 2016

2015

A Fine-Grained Power Gating Control on Linux Monitoring Power Consumption of Processor Functional Units.

[BibT_eX]

[DOI]

IEICE Trans. Electron., 2015

Analyzing and mitigating the impact of manufacturing variability in power-constrained supercomputing.

[BibT_eX]

[DOI]

Proceedings of the International Conference for High Performance Computing, 2015

Runtime multi-optimizations for energy efficient on-chip interconnections1.

[BibT_eX]

[DOI]

Proceedings of the 33rd IEEE International Conference on Computer Design, 2015

A flexible hardware barrier mechanism for many-core processors.

[BibT_eX]

[DOI]

Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015

2014

Unbalanced buffer tree synthesis to suppress ground bounce for fine-grain power gating.

[BibT_eX]

[DOI]

Proceedings of the 2014 International Symposium on System-on-Chip, 2014

Design and evaluation of fine-grained power-gating for embedded microprocessors.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

Design and control methodology for fine grain power gating based on energy characterization and code profiling of microprocessors.

[BibT_eX]

[DOI]

Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014

2013

A Scalable 3D Heterogeneous Multicore with an Inductive ThruChip Interface.

[BibT_eX]

[DOI]

IEEE Micro, 2013

A Prototype System for Many-Core Architecture SMYLEref with FPGA Evaluation Boards.

[BibT_eX]

[DOI]

IEICE Trans. Inf. Syst., 2013

Fine-Grained Run-Tume Power Gating through Co-optimization of Circuit, Architecture, and System Software Design.

[BibT_eX]

[DOI]

IEICE Trans. Electron., 2013

A scalable 3D heterogeneous multi-core processor with inductive-coupling thruchip interface.

[BibT_eX]

[DOI]

Proceedings of the 2013 IEEE Hot Chips 25 Symposium (HCS), 2013

Demonstration of a heterogeneous multi-core processor with 3-D inductive coupling links.

[BibT_eX]

[DOI]

Proceedings of the 23rd International Conference on Field programmable Logic and Applications, 2013

SMYLEref: A reference architecture for manycore-processor SoCs.

[BibT_eX]

[DOI]

Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013

2012

Geyser.

[BibT_eX]

[DOI]

Proceedings of the Handbook of Energy-Aware and Green Computing - Two Volume Set., 2012

Dynamic power control with a heterogeneous multi-core system using a 3-D wireless inductive coupling interconnect.

[BibT_eX]

[DOI]

Proceedings of the 2012 International Conference on Field-Programmable Technology, 2012

CMA-Cube: A scalable reconfigurable accelerator with 3-D wireless inductive coupling interconnect.

[BibT_eX]

[DOI]

Proceedings of the 22nd International Conference on Field Programmable Logic and Applications (FPL), 2012

FLAT: a GPU programming framework to provide embedded MPI.

[BibT_eX]

[DOI]

Proceedings of the 5th Annual Workshop on General Purpose Processing with Graphics Processing Units, 2012

2011

Cool Mega-Arrays: Ultralow-Power Reconfigurable Accelerator Chips.

[BibT_eX]

[DOI]

IEEE Micro, 2011

Design and Implementation Fine-grained Power Gating on Microprocessor Functional Units.

[BibT_eX]

[DOI]

IPSJ Trans. Syst. LSI Des. Methodol., 2011

Cool Mega-Array: A highly energy efficient reconfigurable accelerator.

[BibT_eX]

[DOI]

Proceedings of the 2011 International Conference on Field-Programmable Technology, 2011

SLD-1(Silent Large Datapath): A ultra low power reconfigurable accelerator.

[BibT_eX]

[DOI]

Proceedings of the 2011 IEEE Symposium on Low-Power and High-Speed Chips, 2011

Geyser-2: The second prototype CPU with fine-grained run-time power gating.

[BibT_eX]

[DOI]

Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011

2010

Adaptive power gating for function units in a microprocessor.

[BibT_eX]

[DOI]

Proceedings of the 11th International Symposium on Quality of Electronic Design (ISQED 2010), 2010

Geyser-1: a MIPS R3000 CPU core with fine-grained run-time power gating.

[BibT_eX]

[DOI]

Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010

2009

Energy-Efficient Dynamic Instruction Scheduling Logic Through Instruction Grouping.

[BibT_eX]

[DOI]

Hiroshi Sasaki

IEEE Trans. Very Large Scale Integr. Syst., 2009

Design and Implementation of Fine-Grain Power Gating with Ground Bounce Suppression.

[BibT_eX]

[DOI]

Proceedings of the VLSI Design 2009: Improving Productivity through Higher Abstraction, 2009

Cooperative shared resource access control for low-power chip multiprocessors.

[BibT_eX]

[DOI]

Proceedings of the 2009 International Symposium on Low Power Electronics and Design, 2009

Power-performance modeling of heterogeneous cluster-based web servers.

[BibT_eX]

[DOI]

Proceedings of the 2009 10th IEEE/ACM International Conference on Grid Computing, 2009

2008

A fine-grain dynamic sleep control scheme in MIPS R3000.

[BibT_eX]

[DOI]

Proceedings of the 26th International Conference on Computer Design, 2008

2007

Improving fairness, throughput and energy-efficiency on a chip multiprocessor through DVFS.

[BibT_eX]

[DOI]

Hiroshi Sasaki

SIGARCH Comput. Archit. News, 2007

A High Performance Cluster System Design by Adaptie Power Control.

[BibT_eX]

[DOI]

Yoshimichi Ikeda

Proceedings of the 21th International Parallel and Distributed Processing Symposium (IPDPS 2007), 2007

Power reduction of chip multi-processors using shared resource control cooperating with DVFS.

[BibT_eX]

[DOI]

Proceedings of the 25th International Conference on Computer Design, 2007

Interactive presentation: Task scheduling under performance constraints for reducing the energy consumption of the GALS multi-processor SoC.

[BibT_eX]

[DOI]

Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

An intra-task dvfs technique based on statistical analysis of hardware events.

[BibT_eX]

[DOI]

Proceedings of the 4th Conference on Computing Frontiers, 2007

2006

Design Method of High Performance and Low Power Functional Units Considering Delay Variations.

[BibT_eX]

[DOI]

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2006

2005

Dynamic Instruction Cascading on GALS Microprocessors.

[BibT_eX]

[DOI]

Hiroshi Sasaki

Proceedings of the Integrated Circuit and System Design, 2005

Empirical Study for Optimization of Power-Performance with On-Chip Memory.

[BibT_eX]

[DOI]

Proceedings of the High-Performance Computing - 6th International Symposium, 2005

A Small, Fast and Low-Power Register File by Bit-Partitioning.

[BibT_eX]

[DOI]

Proceedings of the 11th International Conference on High-Performance Computer Architecture (HPCA-11 2005), 2005

2004

SCIMA-SMP: on-chip memory processor architecture for SMP.

[BibT_eX]

[DOI]

Proceedings of the 3rd Workshop on Memory Performance Issues, 2004

Skewed Checkpointing for Tolerating Multi-Node Failures.

[BibT_eX]

[DOI]

Proceedings of the 23rd International Symposium on Reliable Distributed Systems (SRDS 2004), 2004

Dynamic Processor Throttling for Power Efficient Computations.

[BibT_eX]

[DOI]

Proceedings of the Power-Aware Computer Systems, 4th International Workshop, 2004

Data Movement Optimization for Software-Controlled On-Chip Memory.

[BibT_eX]

[DOI]

Motonobu Fujita

Proceedings of the 8th Annual Workshop on Interaction between Compilers and Computer Architecture (INTERACT-8 2004), 2004

2002

Software-controlled on-chip memory for high-performance and low-power computing.

[BibT_eX]

[DOI]

Motonobu Fujita

SIGARCH Comput. Archit. News, 2002

Cache Line Impact on 3D PDE Solvers.

[BibT_eX]

[DOI]

Mitsugu Iwamoto

Proceedings of the High Performance Computing, 4th International Symposium, 2002

Design and evaluation of high performance microprocessor with reconfigurable on-chip memory.

[BibT_eX]

[DOI]

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2002, 2002

2000

Software Controlled Reconfigurable On-Chip Memory for High Performance Computing.

[BibT_eX]

[DOI]

Taisuke Boku

Proceedings of the Intelligent Memory Systems, Second International Workshop, 2000

SCIMA: Software Controlled Integrated Memory Architecture for High Performance Computing.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference On Computer Design: VLSI In Computers & Processors, 2000

An acoustic measure for predicting recognition performance degradation.

[BibT_eX]

[DOI]

Kazuya Takeda