Masaaki Higashitani

According to our database1, Masaaki Higashitani authored at least 15 papers between 2006 and 2014.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2014
A 130.7-mm<sup>2</sup> 2-Layer 32-Gb ReRAM Memory Device in 24-nm Technology.
IEEE J. Solid State Circuits, 2014

2013

2012
A 151-mm<sup>2</sup> 64-Gb 2 Bit/Cell NAND Flash Memory in 24-nm CMOS Technology.
IEEE J. Solid State Circuits, 2012



2011

2009
A 16 Gb 3-Bit Per Cell (X3) NAND Flash Memory on 56 nm Technology With 8 MB/s Write Rate.
IEEE J. Solid State Circuits, 2009

A 34 MB/s MLC Write Throughput 16 Gb NAND With All Bit Line Architecture on 56 nm Technology.
IEEE J. Solid State Circuits, 2009


2008



2007
A 56-nm CMOS 99-mm<sup>2</sup> 8-Gb Multi-Level NAND Flash Memory With 10-MB/s Program Throughput.
IEEE J. Solid State Circuits, 2007

2006
A 146-mm<sup>2</sup> 8-gb multi-level NAND flash memory with 70-nm CMOS technology.
IEEE J. Solid State Circuits, 2006



  Loading...