Martin Saint-Laurent

According to our database, Martin Saint-Laurent authored at least 11 papers between 2001 and 2015.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2015

A 28 nm DSP Powered by an On-Chip LDO for High-Performance and Energy-Efficient Mobile Applications.

Martin Saint-Laurent, Paul Bassett, Ken Lin, Baker Mohammad, Yuhe Wang, Xufeng Chen, Maen Alradaideh, Tom Wernimont, Kartik Ayyar, Dan Bui, Dwight Galbi, Allan Lester, Marzio Pedrali-Noy, Willie Anderson

IEEE J. Solid State Circuits, 2015

Transistor-interconnect mobile system-on-chip co-design method for holistic battery energy minimization.

N. N. Mojumder, Seung Chul Song, K. Rim, J. Xu, Joseph Wang, J. Zhu, Milena Vratonjic, K. Lin, Martin Saint-Laurent, Paul Bassett, Geoffrey Yeap

Proceedings of the Symposium on VLSI Circuits, 2015

Power-aware multi-voltage custom memory models for enhancing RTL and low power verification.

Vijay Kiran Kalyanam, Martin Saint-Laurent, Jacob A. Abraham

Proceedings of the 33rd IEEE International Conference on Computer Design, 2015

2014

10.1 A 28nm DSP powered by an on-chip LDO for high-performance and energy-efficient mobile applications.

Martin Saint-Laurent, Paul Bassett, Ken Lin, Yuhe Wang, Son Le, Xufeng Chen, Maen Alradaideh, Tom Wernimont, Kartik Ayyar, Dan Bui, Dwight Galbi, Allan Lester, Willie Anderson

Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014

2012

Energy efficient design techniques for a digital signal processor.

Paul Bassett, Martin Saint-Laurent

Proceedings of the IEEE International Conference on IC Design & Technology, 2012

2010

A low-power clock gating cell optimized for low-voltage operation in a 45-nm technology.

Martin Saint-Laurent, Animesh Datta

Proceedings of the 2010 International Symposium on Low Power Electronics and Design, 2010

2008

Cache Design for Low Power and High Yield.

Baker Mohammad, Martin Saint-Laurent, Paul Bassett, Jacob A. Abraham

Proceedings of the 9th International Symposium on Quality of Electronic Design (ISQED 2008), 2008

2007

A Model for Interlevel Coupling Noise in Multilevel Interconnect Structures.

Martin Saint-Laurent

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007

A 65-nm pulsed latch with a single clocked transistor.

Martin Saint-Laurent, Baker Mohammad, Paul Bassett

Proceedings of the 2007 International Symposium on Low Power Electronics and Design, 2007

2002

Optimal Sequencing Energy Allocation for CMOS Integrated Systems.

Martin Saint-Laurent, Vojin G. Oklobdzija, Simon S. Singh, Madhavan Swaminathan

Proceedings of the 3rd International Symposium on Quality of Electronic Design, 2002

2001

On The Micro-architectural Impact of Clock Distribution Using Multiple PLLs.

Martin Saint-Laurent, Madhavan Swaminathan, James D. Meindl

Proceedings of the 19th International Conference on Computer Design (ICCD 2001), 2001