Martin Radetzki

According to our database, Martin Radetzki authored at least 80 papers between 1996 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2024

Integer Linear Programming Based Design of Deadlock-Free Routing for Chiplet-Based Systems.

Shuang Liu, Martin Radetzki

Proceedings of the 37th IEEE International System-on-Chip Conference, 2024

2023

Systematic Construction of Deadlock-Free Routing for NoC Using Integer Linear Programming.

Shuang Liu, Martin Radetzki

Proceedings of the 16th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2023

2021

Comprehensive modeling and evaluation of Network-on-Chip performability.

Jie Hou, Martin Radetzki

Proceedings of the Methods and Description Languages for Modelling and Verification of Circuits and Systems, 2021

2019

Power-mode-aware Memory Subsystem Optimization for Low-power System-on-Chip Design.

Manuel Strobel, Martin Radetzki

ACM Trans. Embed. Comput. Syst., 2019

Design-Time Memory Subsystem Optimization for Low-Power Multi-Core Embedded Systems.

Manuel Strobel, Martin Radetzki

Proceedings of the 13th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2019

A Machine Learning Enabled Long-Term Performance Evaluation Framework for NoCs.

Jie Hou, Qi Han, Martin Radetzki

Proceedings of the 13th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2019

Automated Sensor Firmware Development - Generation, Optimization, and Analysis.

Jens Rudolf, Manuel Strobel, Joscha Benz, Christian Haubelt, Martin Radetzki, Oliver Bringmann

Proceedings of the 22nd Workshop Methods and Description Languages for Modelling and Verification of Circuits and Systems, 2019

A Backend Tool for the Integration of Memory Optimizations into Embedded Software.

Manuel Strobel, Martin Radetzki

Proceedings of the 2019 Forum for Specification and Design Languages, 2019

A methodology to compute long-term fault resilience of NoCs under fault-tolerant routing algorithms.

Jie Hou, Martin Radetzki

Proceedings of the 2019 Forum for Specification and Design Languages, 2019

Combined MPSoC Task Mapping and Memory Optimization for Low-Power.

Manuel Strobel, Gereon Führ, Martin Radetzki, Rainer Leupers

Proceedings of the 2019 IEEE Asia Pacific Conference on Circuits and Systems, 2019

2018

Performability Analysis of Mesh-Based NoCs Using Markov Reward Model.

Jie Hou, Martin Radetzki

Proceedings of the 26th Euromicro International Conference on Parallel, 2018

2017

Multi-Layer Diagnosis for Fault-Tolerant Networks-on-Chip.

Gert Schley, Atefe Dalirsani, Marcus Eggenberger, Nadereh Hatami, Hans-Joachim Wunderlich, Martin Radetzki

IEEE Trans. Computers, 2017

Low power memory allocation and mapping for area-constrained systems-on-chips.

Manuel Strobel, Marcus Eggenberger, Martin Radetzki

EURASIP J. Embed. Syst., 2017

Hybrid instruction set simulation for fast and accurate memory access profiling.

Manuel Strobel, Martin Radetzki

Proceedings of the 13th Workshop on Intelligent Solutions in Embedded Systems, 2017

Semi-symbolic operational computation for robust control system design.

Leandro Gil, Martin Radetzki

Proceedings of the 22nd International Conference on Methods and Models in Automation and Robotics, 2017

2016

Reconfigurable fault tolerant routing for networks-on-chip with logical hierarchy.

Gert Schley, Ibrahim Ahmed, Muhammad Afzal, Martin Radetzki

Comput. Electr. Eng., 2016

Globally Asynchronous Locally Synchronous Simulation of NoCs on Many-Core Architectures.

Marcus Eggenberger, Manuel Strobel, Martin Radetzki

Proceedings of the 24th Euromicro International Conference on Parallel, 2016

Orthogonal signal modeling and operational computation of AMS circuits for fast and accurate system simulation.

Leandro Gil, Martin Radetzki

Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

2015

Optimal memory selection for low power embedded systems.

Marcus Eggenberger, Martin Radetzki

Proceedings of the 12th International Workshop on Intelligent Solutions in Embedded Systems, 2015

Fault Tolerant Routing for Hierarchically Organized Networks-on-Chip.

Gert Schley, Martin Radetzki

Proceedings of the 23rd Euromicro International Conference on Parallel, 2015

Multi-Layer Test and Diagnosis for Dependable NoCs.

Hans-Joachim Wunderlich, Martin Radetzki

Proceedings of the 9th International Symposium on Networks-on-Chip, 2015

2014

Editorial introduction - Special issue on languages, models and model based design for embedded systems.

Martin Radetzki, Axel Jantsch

Des. Autom. Embed. Syst., 2014

Asynchronous parallel simulation with transaction events.

Bastian Haetzer, Martin Radetzki

Proceedings of the XIVth International Conference on Embedded Computer Systems: Architectures, 2014

A comparison of parallel systemc simulation approaches at RTL.

Bastian Haetzer, Martin Radetzki

Proceedings of the 2014 Forum on Specification and Design Languages, 2014

SystemC AMS power electronic modeling with ideal instantaneous switches.

Leandro Gil, Martin Radetzki

Proceedings of the 2014 Forum on Specification and Design Languages, 2014

On Covering Structural Defects in NoCs by Functional Tests.

Atefe Dalirsani, Nadereh Hatami, Michael E. Imhof, Marcus Eggenberger, Gert Schley, Martin Radetzki, Hans-Joachim Wunderlich

Proceedings of the 23rd IEEE Asian Test Symposium, 2014

2013

Concurrent and comparative fault simulation in SystemC and its application in robustness evaluation.

Weiyun Lu, Martin Radetzki

Microprocess. Microsystems, 2013

Optimal placement of vertical connections in 3D Network-on-Chip.

Thomas Canhao Xu, Gert Schley, Pasi Liljeberg, Martin Radetzki, Juha Plosila, Hannu Tenhunen

J. Syst. Archit., 2013

Partial Virtual Channel Sharing: A Generic Methodology to Enhance Resource Management and Fault Tolerance in Networks-on-Chip.

Khalid Latif, Amir-Mohammad Rahmani, Ethiopia Nigussie, Tiberiu Seceleanu, Martin Radetzki, Hannu Tenhunen

J. Electron. Test., 2013

Methods for fault tolerance in networks-on-chip.

Martin Radetzki, Chaochao Feng, Xueqian Zhao, Axel Jantsch

ACM Comput. Surv., 2013

Fault Localizing End-to-End Flow Control Protocol for Networks-on-Chip.

Gert Schley, Nikolaos Batzolis, Martin Radetzki

Proceedings of the 21st Euromicro International Conference on Parallel, 2013

Scalable parallel simulation of networks on chip.

Marcus Eggenberger, Martin Radetzki

Proceedings of the 2013 Seventh IEEE/ACM International Symposium on Networks-on-Chip (NoCS), 2013

Power Management for High-Performance Applications on Network-on-Chip-Based Multiprocessors.

Adán Kohler, Martin Radetzki

Proceedings of the 2013 IEEE International Conference on Green Computing and Communications (GreenCom) and IEEE Internet of Things (iThings) and IEEE Cyber, 2013

Simulation analysis and validation.

Frank Oppenheimer, Martin Radetzki

Proceedings of the 2013 Forum on specification and Design Languages, 2013

Systemc transaction level modeling with transaction events.

Bastian Haetzer, Martin Radetzki

Proceedings of the 2013 Forum on specification and Design Languages, 2013

Fine grained adaptive simulation with application to NoCs.

Marcus Eggenberger, Martin Radetzki

Proceedings of the 2013 Forum on specification and Design Languages, 2013

Platform based design.

Jean-Philippe Babau, Martin Radetzki

Proceedings of the 2013 Forum on specification and Design Languages, 2013

2012

Semantics and efficient simulation of accuracy-adaptive TLMs.

Rauf Salimi Khaligh, Martin Radetzki

Des. Autom. Embed. Syst., 2012

Latency-optimized Collectives for High Performance on Intel's Single-chip Cloud Computer.

Adán Kohler, Martin Radetzki

Proceedings of the Many-core Applications Research Community (MARC) Symposium at RWTH Aachen University, 2012

Optimized Reduce for Mesh-Based NoC Multiprocessors.

Adán Kohler, Martin Radetzki

Proceedings of the 26th IEEE International Parallel and Distributed Processing Symposium Workshops & PhD Forum, 2012

Minimal MPI as programming interface for multicore System-on-Chips.

Adán Kohler, Juan Manuel Castillo-Sanchez, Joachim Gross, Martin Radetzki

Proceedings of the Proceeding of the 2012 Forum on Specification and Design Languages, 2012

Low-Latency Collectives for the Intel SCC.

Adán Kohler, Martin Radetzki, Philipp Gschwandtner, Thomas Fahringer

Proceedings of the 2012 IEEE International Conference on Cluster Computing, 2012

2011

Cost-Based Deflection Routing for Intelligent NoC Switches.

Martin Radetzki, Adán Kohler

Proceedings of the Solutions on Embedded Systems, 2011

Optimal distribution of privileged nodes in networks-on-chip.

Gert Schley, Martin Radetzki

Proceedings of the Ninth Workshop on Intelligent Solutions in Embedded Systems, 2011

A metamodel and semantics for transaction level modeling.

Rauf Salimi Khaligh, Martin Radetzki

Proceedings of the 2011 Forum on Specification & Design Languages, 2011

A case study on message-based discrete event simulation for Transaction Level Modeling.

Bastian Haetzer, Martin Radetzki

Proceedings of the 2011 Forum on Specification & Design Languages, 2011

Fault-Tolerant Differential Q Routing in Arbitrary NoC Topologies.

Martin Radetzki

Proceedings of the IEEE/IFIP 9th International Conference on Embedded and Ubiquitous Computing, 2011

Practical embedded systems engineering syllabus for graduate students with multidisciplinary backgrounds.

Bastian Haetzer, Gert Schley, Rauf Salimi Khaligh, Martin Radetzki

Proceedings of the 6th Workshop on Embedded Systems Education, 2011

Efficient Fault Simulation of SystemC Designs.

Weiyun Lu, Martin Radetzki

Proceedings of the 14th Euromicro Conference on Digital System Design, 2011

2010

Fault Tolerant Network on Chip Switching With Graceful Performance Degradation.

Adán Kohler, Gert Schley, Martin Radetzki

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010

Degradability Enabled Routing for Network-on-Chip Switches (Routingverfahren zur Unterstützung der Degradierbarkeit von Network-on-Chip Switches).

Gert Schley, Martin Radetzki, Adán Kohler

it Inf. Technol., 2010

A Dynamic Load Balancing Method for Parallel Simulation of Accuracy Adaptive TLMs.

Rauf Salimi Khaligh, Martin Radetzki

Proceedings of the 2010 Forum on specification & Design Languages, 2010

Modeling constructs and kernel for parallel simulation of accuracy adaptive TLMs.

Rauf Salimi Khaligh, Martin Radetzki

Proceedings of the Design, Automation and Test in Europe, 2010

2009

An intelligent deflection router for networks-on-chip.

Martin Radetzki, Adán Kohler

Proceedings of the Seventh Workshop on Intelligent solutions in Embedded Systems, 2009

Fault-tolerant architecture and deflection routing for degradable NoC switches.

Adán Kohler, Martin Radetzki

Proceedings of the Third International Symposium on Networks-on-Chips, 2009

Modellierung und Simulation von Networks-on-Chip mit OSCI TLM2.

Adán Kohler, Martin Radetzki

Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2009

Efficient Parallel Transaction Level Simulation by Exploiting Temporal Decoupling.

Rauf Salimi Khaligh, Martin Radetzki

Proceedings of the Analysis, 2009

A SystemC TLM2 model of communication in wormhole switched Networks-On-Chip.

Adán Kohler, Martin Radetzki

Proceedings of the Forum on specification and Design Languages, 2009

Test exploration and validation using transaction level models.

Michael A. Kochte, Christian G. Zoellin, Michael E. Imhof, Rauf Salimi Khaligh, Martin Radetzki, Hans-Joachim Wunderlich, Stefano Di Carlo, Paolo Prinetto

Proceedings of the Design, Automation and Test in Europe, 2009

2008

A data traffic efficient H.264 deblocking IP.

Weining Hao, Martin Radetzki

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

Adaptive Interconnect Models for Transaction-Level Simulation.

Rauf Salimi Khaligh, Martin Radetzki

Proceedings of the Languages for Embedded Systems and their Applications, 2008

A Latency, Preemption and Data Transfer Accurate Adaptive Transaction Level Model for Efficient Simulation of Pipelined Buses.

Rauf Salimi Khaligh, Martin Radetzki

Proceedings of the Forum on specification and Design Languages, 2008

Accuracy-Adaptive Simulation of Transaction Level Models.

Martin Radetzki, Rauf Salimi Khaligh

Proceedings of the Design, Automation and Test in Europe, 2008

2007

Modellierung auf der Transaktionsebene unter Nutzung des Entwurfsmusters des aktiven Objekts.

Martin Radetzki

Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2007

Efficient and Extensible Transaction Level Modeling Based on an Object Oriented Model of Bus Transactions.

Rauf Salimi Khaligh, Martin Radetzki

Proceedings of the Embedded System Design: Topics, Techniques and Trends, IFIP TC10 Working Conference: International Embedded Systems Symposium (IESS), May 30, 2007

Modelling Alternatives for Cycle Approximate Bus TLMs.

Martin Radetzki, Rauf Salimi Khaligh

Proceedings of the Forum on specification and Design Languages, 2007

2006

SystemC TLM Transaction Modelling and Dispatch for Active Object.

Martin Radetzki

Proceedings of the Forum on specification and Design Languages, 2006

2004

Intelligent IP retrieval driven by application requirements.

Martin Schaaf, Andrea Freßmann, Rainer Maximini, Ralph Bergmann, Alexander Tartakovski, Martin Radetzki

Integr., 2004

IPQ: IP Qualification for Efficient System Design.

Hans-Jürgen Brand, Steffen Rülke, Martin Radetzki

Proceedings of the 5th International Symposium on Quality of Electronic Design (ISQED 2004), 2004

Measurement of IP Qualification Costs and Benefits.

Andreas Vörg, Martin Radetzki, Wolfgang Rosenstiel

Proceedings of the 2004 Design, 2004

2003

sciPROVE: C++ Based Verification Environment for IP and SoC Design1.

U. Badelt, H. Kühl, Martin Radetzki

Proceedings of the Forum on specification and Design Languages, 2003

2002

Qualität und Qualitätssicherung wiederverwendbarer Schaltungsbeschreibungen (Quality and Quality Assurance of Reusable Circuit Descriptions).

Martin Radetzki

Informationstechnik Tech. Inform., 2002

A Qualification Platform for Design Reuse.

Ralf Seepold, Natividad Martínez Madrid, Andreas Vörg, Wolfgang Rosenstiel, Martin Radetzki, Peter Neumann, Jürgen Haase

Proceedings of the 3rd International Symposium on Quality of Electronic Design, 2002

2000

Synthesis of digital circuits from object oriented specifications.

Martin Radetzki

PhD thesis, 2000

1999

Data Type Analysis for Hardware Synthesis from Object-Oriented Models.

Martin Radetzki, Ansgar Stammermann, Wolfram Putzke-Röming, Wolfgang Nebel

Proceedings of the 1999 Design, 1999

1998

A Unified Approach to Object-Oriented VHDL.

Martin Radetzki, Wolfram Putzke-Röming, Wolfgang Nebel

J. Inf. Sci. Eng., 1998

Übersetzung von Objektorientiertem VHDL nach Standard VHDL.

Martin Radetzki, Wolfram Putzke-Röming, Wolfgang Nebel

Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 1998

A Flexible Message Passing Mechanism for Objective VHDL.

Wolfram Putzke-Röming, Martin Radetzki, Wolfgang Nebel

Proceedings of the 1998 Design, 1998

ATM Cell Modelling using Objective VHDL.

Alberto Allara, Massimo Bombana, Patrizia Cavalloro, Wolfgang Nebel, Wolfram Putzke-Röming, Martin Radetzki

Proceedings of the ASP-DAC '98, 1998

1996

Development of a Telephone Answering Machine in a Lab - FPGAs in Education.

Guido Schumacher, Bernhard Josko, Gerhard Wagner, Martin Radetzki

Proceedings of the Field-Programmable Logic, 1996