Martin Palkovic
According to our database1,
Martin Palkovic
authored at least 37 papers
between 2002 and 2017.
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Bibliography
2017
Proceedings of the 2017 International Conference on Embedded Computer Systems: Architectures, 2017
2016
Autotuning and adaptivity approach for energy efficient Exascale HPC systems: The ANTAREX approach.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016
Proceedings of the ACM International Conference on Computing Frontiers, CF'16, 2016
2015
ANTAREX - AutoTuning and Adaptivity appRoach for Energy Efficient eXascale HPC Systems.
Proceedings of the 18th IEEE International Conference on Computational Science and Engineering, 2015
2013
Design Flow for Silicon Chip Implementing Novel Platform Architecture for Wireless Communication.
Int. J. Embed. Real Time Commun. Syst., 2013
2012
DART - a High Level Software-Defined Radio Platform Model for Developing the Run-Time Controller.
J. Signal Process. Syst., 2012
J. Low Power Electron., 2012
Proceedings of the 2012 International Symposium on System on Chip, 2012
Parallel paradigms and run-time management techniques for many-core architectures: the 2PARMA approach.
Proceedings of the 2012 Interconnection Network Architecture, 2012
Partitioning and Assignment Exploration for Multiple Modes of IEEE 802.11n Modem on Heterogeneous MPSoC Platforms.
Proceedings of the 15th Euromicro Conference on Digital System Design, 2012
2011
Proceedings of the IEEE 9th Symposium on Application Specific Processors, 2011
Invited paper: Parallel programming and run-time resource management framework for many-core platforms: The 2PARMA approach.
Proceedings of the 6th International Workshop on Reconfigurable Communication-centric Systems-on-Chip, 2011
Dart - a high level software-defined radio platform model for developing the run-time controller.
Proceedings of the IEEE International Conference on Acoustics, 2011
2010
IEEE Signal Process. Mag., 2010
J. Electron. Test., 2010
2PARMA: Parallel Paradigms and Run-Time Management Techniques for Many-Core Architectures.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2010
2PARMA: Parallel Paradigms and Run-time Management Techniques for Many-Core Architectures.
Proceedings of the VLSI 2010 Annual Symposium - Selected papers, 2010
2009
ACM Trans. Design Autom. Electr. Syst., 2009
Dealing with data dependent conditions to enable general global source code transformations.
Int. J. Embed. Syst., 2009
Proceedings of the Parallel Computing: From Multicores and GPU's to Petascale, 2009
System-level power/performance evaluation of 3D stacked DRAMs for mobile applications.
Proceedings of the Design, Automation and Test in Europe, 2009
2008
Guidance of Loop Ordering for Reduced Memory Usage in Signal Processing Applications.
J. Signal Process. Syst., 2008
Storage Estimation and Design Space Exploration Methodologies for the Memory Management of Signal Processing Applications.
J. Signal Process. Syst., 2008
Proceedings of the 11th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2008), 2008
2007
Incremental hierarchical memory size estimation for steering of loop transformations.
ACM Trans. Design Autom. Electr. Syst., 2007
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007
Proceedings of the International Symposium on System-on-Chip, 2007
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007
2006
Polyhedral space generation and memory estimation from interface and memory models of real-time video systems.
J. Syst. Softw., 2006
J. Low Power Electron., 2006
Hierarchical memory size estimation for loop fusion and loop shifting in data-dominated applications.
Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006
Proceedings of the 2006 IEEE International Conference on Application-Specific Systems, 2006
2005
Proceedings of the 9th International Workshop on Software and Compilers for Embedded Systems, Dallas, Texas, USA, September 29, 2005
2004
Proceedings of the 2004 Euromicro Symposium on Digital Systems Design (DSD 2004), Architectures, Methods and Tools, 31 August, 2004
2002
Systematic Address and Control Code Transformations for Performance Optimisation of a MPEG-4 Video Decoder.
Proceedings of the 7th Asia and South Pacific Design Automation Conference (ASP-DAC 2002), 2002
Systematic Power-Performance Trade-Off in MPEG-4 by Means of Selective Function Inlining Steered by Address Optimization Opportunities.
Proceedings of the 2002 Design, 2002