Martin Omaña
Orcid: 0000-0001-8976-5365Affiliations:
- University of Bologna, Department of Electrical, Electronic and Information Engineering, Italy
According to our database1,
Martin Omaña
authored at least 72 papers
between 2003 and 2024.
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Bibliography
2024
Proceedings of the 30th IEEE International Symposium on On-Line Testing and Robust System Design, 2024
Silent Data Corruption and Reliability Risks due to Faults Affecting High Performance Microprocessors' Caches.
Proceedings of the 30th IEEE International Symposium on On-Line Testing and Robust System Design, 2024
2023
RISC-V-Based Platforms for HPC: Analyzing Non-functional Properties for Future HPC and Big-Data Clusters.
Proceedings of the Embedded Computer Systems: Architectures, Modeling, and Simulation, 2023
2022
Microprocess. Microsystems, March, 2022
Reliability Risks Due to Faults Affecting Selectors of ReRAMs and Possible Solutions.
IEEE Trans. Emerg. Top. Comput., 2022
Proceedings of the 23rd IEEE Latin American Test Symposium, 2022
Proceedings of the 28th IEEE International Symposium on On-Line Testing and Robust System Design, 2022
2021
ST-CAC: a low-cost crosstalk avoidance coding mechanism based on three-valued numerical system.
J. Supercomput., 2021
J. Electron. Test., 2021
2019
IEEE Trans. Very Large Scale Integr. Syst., 2019
Impact of Bias Temperature Instability (BTI) Aging Phenomenon on Clock Deskew Buffers.
J. Electron. Test., 2019
2018
IEEE Trans. Emerg. Top. Comput., 2018
2017
IEEE Trans. Very Large Scale Integr. Syst., 2017
IEEE Trans. Computers, 2017
2016
Low-Cost and High-Reduction Approaches for Power Droop during Launch-On-Shift Scan-Based Logic BIST.
IEEE Trans. Computers, 2016
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016
2015
IEEE Trans. Very Large Scale Integr. Syst., 2015
IEEE Trans. Very Large Scale Integr. Syst., 2015
IEEE Trans. Very Large Scale Integr. Syst., 2015
Proceedings of the 24th IEEE Asian Test Symposium, 2015
2014
Proceedings of the 2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2014
2013
Faults Affecting Energy-Harvesting Circuits of Self-Powered Wireless Sensors and Their Possible Concurrent Detection.
IEEE Trans. Very Large Scale Integr. Syst., 2013
IEEE Trans. Computers, 2013
Low Cost Concurrent Error Detection Strategy for the Control Logic of High Performance Microprocessors and Its Application to the Instruction Decoder.
J. Electron. Test., 2013
Proceedings of the 18th IEEE European Test Symposium, 2013
2012
IEEE Trans. Computers, 2012
Faults affecting the control blocks of PV arrays and techniques for their concurrent detection.
Proceedings of the 2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2012
High-reliability fault tolerant digital systems in nanometric technologies: Characterization and design methodologies.
Proceedings of the 2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2012
2011
Low-Cost Dynamic Compensation Scheme for Local Clocks of Next Generation High Performance Microprocessors.
IEEE Trans. Very Large Scale Integr. Syst., 2011
Proceedings of the 2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2011
Proceedings of the 2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2011
2010
Proceedings of the 2010 East-West Design & Test Symposium, 2010
Proceedings of the 25th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2010
On-die Ring Oscillator Based Measurement Scheme for Process Parameter Variations and Clock Jitter.
Proceedings of the 25th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2010
Low cost and low intrusive approach to test on-line the scheduler of high performance microprocessors.
Proceedings of the 7th Conference on Computing Frontiers, 2010
Proceedings of the 7th Conference on Computing Frontiers, 2010
2009
IEEE Trans. Very Large Scale Integr. Syst., 2009
Proceedings of the 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2009
Concurrent Detection of Faults Affecting Energy Harvesting Circuits of Self-Powered Wearable Sensors.
Proceedings of the 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2009
2008
J. Electron. Test., 2008
Function-Inherent Code Checking: A New Low Cost On-Line Testing Approach for High Performance Microprocessor Control Logic.
Proceedings of the 13th European Test Symposium, 2008
Proceedings of the 23rd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2008), 2008
2007
IEEE Trans. Computers, 2007
Proceedings of the 25th IEEE VLSI Test Symposium (VTS 2007), 2007
Proceedings of the 2007 IEEE International Test Conference, 2007
2006
Proceedings of the 12th IEEE International On-Line Testing Symposium (IOLTS 2006), 2006
Proceedings of the 12th IEEE International On-Line Testing Symposium (IOLTS 2006), 2006
Proceedings of the 9th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2006), 2006
Low-cost and highly reliable detector for transient and crosstalk faults affecting FPGA interconnects.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006
2005
IEEE Trans. Instrum. Meas., 2005
Proceedings of the 23rd IEEE VLSI Test Symposium (VTS 2005), 2005
On the Selection of Unidirectional Error Detecting Codes for Self-Checking Circuits' Area Overhead and Performance Optimization.
Proceedings of the 11th IEEE International On-Line Testing Symposium (IOLTS 2005), 2005
Proceedings of the 11th IEEE International On-Line Testing Symposium (IOLTS 2005), 2005
Proceedings of the 20th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2005), 2005
Proceedings of the 20th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2005), 2005
2004
J. Electron. Test., 2004
Risks Associated with Faults within Test Pattern Compactors and Their Implications on Testing.
Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004
Proceedings of the 10th IEEE International On-Line Testing Symposium (IOLTS 2004), 2004
Proceedings of the 10th IEEE International On-Line Testing Symposium (IOLTS 2004), 2004
Proceedings of the 19th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2004), 2004
Proceedings of the 2004 Design, 2004
Fault secureness need for next generation high performance microprocessor design for testability structures.
Proceedings of the First Conference on Computing Frontiers, 2004
2003
Proceedings of the Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September, 2003
Proceedings of the 9th IEEE International On-Line Testing Symposium (IOLTS 2003), 2003
Proceedings of the 18th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2003), 2003
Proceedings of the 2003 Design, 2003