Martín Letras

Orcid: 0000-0002-1429-8982

Affiliations:
  • University of Erlangen-Nuremberg, Department of Computer Science, Germany


According to our database1, Martín Letras authored at least 18 papers between 2015 and 2024.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Bibliography

2024
A novel partition strategy for efficient implementation of 3D Cellular Genetic Algorithms.
Microprocess. Microsystems, 2024

Exploring Multi-Reader Buffers and Channel Placement During Dataflow Network Mapping to Heterogeneous Many-Core Systems.
IEEE Access, 2024

2023
Efficient Table-based Function Approximation on FPGAs Using Interval Splitting and BRAM Instantiation.
ACM Trans. Embed. Comput. Syst., July, 2023

Throughput and Memory Optimization for Parallel Implementations of Dataflow Networks Using Multi-Reader Buffers.
Proceedings of the Fourth Workshop on Next Generation Real-Time Embedded Systems, 2023

2022
FPGA/GPU-based Acceleration for Frequent Itemsets Mining: A Comprehensive Review.
ACM Comput. Surv., 2022

2021
Multi-objective Optimization of Mapping Dataflow Applications to MPSoCs Using a Hybrid Evaluation Combining Analytic Models and Measurements.
ACM Trans. Design Autom. Electr. Syst., 2021

Decision Tree-based Throughput Estimation to Accelerate Design Space Exploration for Multi-Core Applications.
Proceedings of the Methods and Description Languages for Modelling and Verification of Circuits and Systems, 2021

2020
On the design of hardware architectures for parallel frequent itemsets mining.
Expert Syst. Appl., 2020

2019
Compilation of Dataflow Applications for Multi-Cores using Adaptive Multi-Objective Optimization.
ACM Trans. Design Autom. Electr. Syst., 2019

Using hashing and lexicographic order for Frequent Itemsets Mining on data streams.
J. Parallel Distributed Comput., 2019

On the Analytic Evaluation of Schedules via Max-Plus Algebra for DSE of Multi-Core Architectures.
Proceedings of the 22nd International Workshop on Software and Compilers for Embedded Systems, 2019

2018
Model-Based Design Automation of Hardware/Software Co-Designs for Xilinx Zynq PSoCs.
Proceedings of the 2018 International Conference on ReConFigurable Computing and FPGAs, 2018

2017
Automatic Conversion of Simulink Models to SysteMoC Actor Networks.
Proceedings of the 20th International Workshop on Software and Compilers for Embedded Systems, 2017

Approximate frequent itemsets mining on data streams using hashing and lexicographie order in hardware.
Proceedings of the 8th IEEE Latin American Symposium on Circuits & Systems, 2017

High-Level Synthesis for Hardware/Software Co-Design of Distributed Smart Camera Systems.
Proceedings of the 11th International Conference on Distributed Smart Cameras, 2017

2016
A scalable and customizable processor array for implementing cellular genetic algorithms.
Neurocomputing, 2016

Hardware Architectures for Frequent Itemset Mining Based on Equivalence Classes Partitioning.
Proceedings of the 2016 IEEE International Parallel and Distributed Processing Symposium Workshops, 2016

2015
An Empirical Analysis on Dimensionality in Cellular Genetic Algorithms.
Proceedings of the Genetic and Evolutionary Computation Conference, 2015


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