Martin Lefebvre
Orcid: 0000-0002-9303-5311Affiliations:
- Université catholique de Louvain, ICTEAM Institute, Louvain-la-Neuve, Belgium
According to our database1,
Martin Lefebvre
authored at least 14 papers
between 2019 and 2024.
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Bibliography
2024
A 2.5-nA Area-Efficient Temperature-Independent 176-/82-ppm/°C CMOS-Only Current Reference in 0.11- μ m Bulk and 22-nm FD-SOI.
IEEE J. Solid State Circuits, November, 2024
A nA-Range Area-Efficient Sub-100-ppm/°C Peaking Current Reference Using Forward Body Biasing in 0.11-μm Bulk and 22-nm FD-SOI.
CoRR, 2024
A 2.5-nA Area-Efficient Temperature-Independent 176-/82-ppm/°C CMOS-Only Current Reference in 0.11-μm Bulk and 22-nm FD-SOI.
CoRR, 2024
A Mixed-Signal Near-Sensor Convolutional Imager SoC with Charge-Based 4b-Weighted 5-to-84-TOPS/W MAC Operations for Feature Extraction and Region-of-Interest Detection.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2024
2023
IMPACT: A 1-to-4b 813-TOPS/W 22-nm FD-SOI Compute-in-Memory CNN Accelerator Featuring a 4.2-POPS/W 146-TOPS/mm<sup>2</sup> CIM-SRAM With Multi-Bit Analog Batch-Normalization.
IEEE J. Solid State Circuits, 2023
A 1.1-/0.9-nA Temperature-Independent 213-/565-ppm/°C Self-Biased CMOS-Only Current Reference in 65-nm Bulk and 22-nm FDSOI.
IEEE J. Solid State Circuits, 2023
A 1.1- / 0.9-nA Temperature-Independent 213- / 565-ppm/$^\circ$C Self-Biased CMOS-Only Current Reference in 65-nm Bulk and 22-nm FDSOI.
CoRR, 2023
2022
A Family of Current References Based on 2T Voltage References: Demonstration in 0.18-μm With 0.1-nA PTAT and 1.1-μA CWT 38-ppm/°C Designs.
IEEE Trans. Circuits Syst. I Regul. Pap., 2022
A 0.9-nA Temperature-Independent 565-ppm/°C Self-Biased Current Reference in 22-nm FDSOI.
Proceedings of the 48th IEEE European Solid State Circuits Conference, 2022
A 1-to-4b 16.8-POPS/W 473-TOPS/mm2 6T-based In-Memory Computing SRAM in 22nm FD-SOI with Multi-Bit Analog Batch-Normalization.
Proceedings of the 48th IEEE European Solid State Circuits Conference, 2022
2021
SleepRider: a 5.5μW/MHz Cortex-M4 MCU in 28nm FD-SOI with ULP SRAM, Biomedical AFE and Fully-Integrated Power, Clock and Back-Bias Management.
Proceedings of the 2021 Symposium on VLSI Circuits, Kyoto, Japan, June 13-19, 2021, 2021
A 0.2-to-3.6TOPS/W Programmable Convolutional Imager SoC with In-Sensor Current-Domain Ternary-Weighted MAC Operations for Feature Extraction and Region-of-Interest Detection.
Proceedings of the IEEE International Solid-State Circuits Conference, 2021
2019
A 0.086-mm<sup>2</sup> 12.7-pJ/SOP 64k-Synapse 256-Neuron Online-Learning Digital Spiking Neuromorphic Processor in 28-nm CMOS.
IEEE Trans. Biomed. Circuits Syst., 2019
Learning without feedback: Direct random target projection as a feedback-alignment algorithm with layerwise feedforward training.
CoRR, 2019