Martin Kumm

IEEE Trans. Circuits Syst. I Regul. Pap., January, 2024

Multiplier Design Addressing Area-Delay Trade-offs by using DSP and Logic resources on FPGAs.

[BibT_eX]

[DOI]

Proceedings of the 35th IEEE International Conference on Application-specific Systems, 2024

Small Logic-based Multipliers with Incomplete Sub-Multipliers for FPGAs.

[BibT_eX]

[DOI]

Proceedings of the 31st IEEE Symposium on Computer Arithmetic, 2024

2023

Towards Globally Optimal Design of Multipliers for FPGAs.

[BibT_eX]

[DOI]

IEEE Trans. Computers, May, 2023

Design of Optimal Multiplierless FIR Filters With Minimal Number of Adders.

[BibT_eX]

[DOI]

Anastasia Volkova

Silviu-Ioan Filip

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., February, 2023

More AddNet: A deeper insight into DNNs using FPGA-optimized multipliers.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2023

Hardware-Optimal Digital FIR Filters: One ILP to Rule Them all and in Faithfulness Bind Them.

[BibT_eX]

[DOI]

Proceedings of the 57th Asilomar Conference on Signals, Systems, and Computers, ACSSC 2023, Pacific Grove, CA, USA, October 29, 2023

2022

Hardware-Aware Design of Multiplierless Second-Order IIR Filters With Minimum Adders.

[BibT_eX]

[DOI]

IEEE Trans. Signal Process., 2022

Truncated Multiple Constant Multiplication with Minimal Number of Full Adders.

[BibT_eX]

[DOI]

Rémi Garcia

Anastasia Volkova

Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

Resource Optimal Squarers for FPGAs.

[BibT_eX]

[DOI]

Florent de Dinechin

Proceedings of the 32nd International Conference on Field-Programmable Logic and Applications, 2022

Hardware-Aware Quantization for Multiplierless Neural Network Controllers.

[BibT_eX]

[DOI]

Proceedings of the IEEE Asia Pacific Conference on Circuit and Systems, 2022

2021

Towards Arithmetic-Centered Filter Design.

[BibT_eX]

[DOI]

Proceedings of the 28th IEEE Symposium on Computer Arithmetic, 2021

Resource Optimal Truncated Multipliers for FPGAs.

[BibT_eX]

[DOI]

Florent de Dinechin

Proceedings of the 28th IEEE Symposium on Computer Arithmetic, 2021

2020

AddNet: Deep Neural Networks Using FPGA-Optimized Multipliers.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2020

Comparison of Arithmetic Number Formats for Inference in Sum-Product Networks on FPGAs.

[BibT_eX]

[DOI]

Proceedings of the 28th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2020

Modulo Scheduling with Rational Initiation Intervals in Custom Hardware Design.

[BibT_eX]

[DOI]

Proceedings of the 25th Asia and South Pacific Design Automation Conference, 2020

Heuristics for the Design of Large Multipliers for FPGAs.

[BibT_eX]

[DOI]

Keanu Kullmann

Proceedings of the 27th IEEE Symposium on Computer Arithmetic, 2020

2019

Unrolling Ternary Neural Networks.

[BibT_eX]

[DOI]

ACM Trans. Reconfigurable Technol. Syst., 2019

World's Fastest FFT Architectures: Breaking the Barrier of 100 GS/s.

[BibT_eX]

[DOI]

Mario Garrido

IEEE Trans. Circuits Syst. I Regul. Pap., 2019

Isomorphic Subgraph-based Problem Reduction for Resource Minimal Modulo Scheduling.

[BibT_eX]

[DOI]

Proceedings of the 2019 International Conference on ReConFigurable Computing and FPGAs, 2019

Reconfigurable Convolutional Kernels for Neural Networks on FPGAs.

[BibT_eX]

[DOI]

Proceedings of the 2019 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2019

Design-Space Exploration with Multi-Objective Resource-Aware Modulo Scheduling.

[BibT_eX]

[DOI]

Julian Oppermann

Patrick Sittel

Melanie Reuter-Oppermann

Andreas Koch

Oliver Sinnen

Proceedings of the Euro-Par 2019: Parallel Processing, 2019

Efficient Error-Tolerant Quantized Neural Network Accelerators.

[BibT_eX]

[DOI]

Proceedings of the 2019 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2019

Table-Based versus Shift-And-Add Constant Multipliers for FPGAs.

[BibT_eX]

[DOI]

Proceedings of the 26th IEEE Symposium on Computer Arithmetic, 2019

2018

Optimal Single Constant Multiplication Using Ternary Adders.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2018

Optimal Constant Multiplication Using Integer Linear Programming.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2018

Optimal Shift Reassignment in Reconfigurable Constant Multiplication Circuits.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

Advanced Compressor Tree Synthesis for FPGAs.

[BibT_eX]

[DOI]

Johannes Kappauf

IEEE Trans. Computers, 2018

ScaLP: A Light-Weighted (MI)LP-Library.

[BibT_eX]

[DOI]

Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen, 2018

Constant Matrix Multiplication with Ternary Adders.

[BibT_eX]

[DOI]

Proceedings of the 25th IEEE International Conference on Electronics, Circuits and Systems, 2018

ILP-Based Modulo Scheduling and Binding for Register Minimization.

[BibT_eX]

[DOI]

Proceedings of the 28th International Conference on Field Programmable Logic and Applications, 2018

Karatsuba with Rectangular Multipliers for FPGAs.

[BibT_eX]

[DOI]

Proceedings of the 25th IEEE Symposium on Computer Arithmetic, 2018

2017

Reconfigurable Constant Multiplication for FPGAs.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017

Optimization of Constant Matrix Multiplication with Low Power and High Throughput.

[BibT_eX]

[DOI]

Martin Hardieck

IEEE Trans. Computers, 2017

High-Level Synthesis for Model-Based Design with Automatic Folding including Combined Common Subcircuits.

[BibT_eX]

Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen, 2017

Model-based hardware design based on compatible sets of isomorphic subgraphs.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Field Programmable Technology, 2017

Resource Optimal Design of Large Multipliers for FPGAs.

[BibT_eX]

[DOI]

Proceedings of the 24th IEEE Symposium on Computer Arithmetic, 2017

2016

Multiple constant multiplication optimizations for field programmable gate arrays.

[BibT_eX]

[DOI]

PhD thesis, 2016

CORDIC II: A New Improved CORDIC Algorithm.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2016

Comment on "High Efficiency Generalized Parallel Counters for Look-Up Table Based FPGAs".

[BibT_eX]

[DOI]

Int. J. Reconfigurable Comput., 2016

Efficient sum of absolute difference computation on FPGAs.

[BibT_eX]

[DOI]

Marco Kleinlein

Proceedings of the 26th International Conference on Field Programmable Logic and Applications, 2016

2015

Model-based Hardware Design for FPGAs using Folding Transformations based on Subcircuits.

[BibT_eX]

[DOI]

Charles-Frederic Müller

CoRR, 2015

Efficient structural adder pipelining in transposed form FIR filters.

[BibT_eX]

[DOI]

Proceedings of the 2015 IEEE International Conference on Digital Signal Processing, 2015

An Efficient Softcore Multiplier Architecture for Xilinx FPGAs.

[BibT_eX]

[DOI]

Shahid Abbas

Proceedings of the 22nd IEEE Symposium on Computer Arithmetic, 2015

2014

Dynamically Reconfigurable Constant Multiplication on FPGAs.

[BibT_eX]

Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen, 2014

Efficient High Speed Compression Trees on Xilinx FPGAs.

[BibT_eX]

Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen, 2014

Pipelined reconfigurable multiplication with constants on FPGAs.

[BibT_eX]

[DOI]

Proceedings of the 24th International Conference on Field Programmable Logic and Applications, 2014

Pipelined compressor tree optimization using integer linear programming.

[BibT_eX]

[DOI]

Proceedings of the 24th International Conference on Field Programmable Logic and Applications, 2014

2013

FIR filter optimization for video processing on FPGAs.

[BibT_eX]

[DOI]

EURASIP J. Adv. Signal Process., 2013

Dynamically reconfigurable FIR filter architectures with fast reconfiguration.

[BibT_eX]

[DOI]

Proceedings of the 2013 8th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC), 2013

Reconfigurable FIR filter using distributed arithmetic on FPGAs.

[BibT_eX]

[DOI]

Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

Partial LUT size analysis in distributed arithmetic FIR Filters on FPGAs.

[BibT_eX]

[DOI]

Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

Multiple constant multiplication with ternary adders.

[BibT_eX]

[DOI]

Proceedings of the 23rd International Conference on Field programmable Logic and Applications, 2013

2012

Pipelined adder graph optimization for high speed multiple constant multiplication.

[BibT_eX]

[DOI]

Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

Hybrid multiple constant multiplication for FPGAs.

[BibT_eX]

[DOI]

Proceedings of the 19th IEEE International Conference on Electronics, Circuits and Systems, 2012

Area estimation of look-up table based fixed-point computations on the example of a real-time high dynamic range imaging system.

[BibT_eX]

[DOI]

Proceedings of the 22nd International Conference on Field Programmable Logic and Applications (FPL), 2012

Reduced complexity single and multiple constant multiplication in floating point precision.

[BibT_eX]

[DOI]

Katharina Liebisch

Proceedings of the 22nd International Conference on Field Programmable Logic and Applications (FPL), 2012

2011

High speed low complexity FPGA-based FIR filters using pipelined adder graphs.

[BibT_eX]

[DOI]

Proceedings of the 2011 International Conference on Field-Programmable Technology, 2011

2010

An FPGA-Based Linear All-Digital Phase-Locked Loop.

[BibT_eX]

[DOI]

Harald Klingbeil

IEEE Trans. Circuits Syst. I Regul. Pap., 2010

2008

Digital hilbert transformers for FPGA-based phase-locked loops.

[BibT_eX]

[DOI]