Martin Krcma

According to our database, Martin Krcma authored at least 18 papers between 2015 and 2021.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2021

Testing Embedded Software Through Fault Injection: Case Study on Smart Lock.

Jakub Lojda, Richard Panek, Jakub Podivinsky, Ondrej Cekan, Martin Krcma, Zdenek Kotásek

Proceedings of the 22nd IEEE Latin American Test Symposium, 2021

2020

Evaluation Platform For Testing Fault Tolerance: Testing Reliability of Smart Electronic Locks.

Jakub Podivinsky, Jakub Lojda, Richard Panek, Ondrej Cekan, Martin Krcma, Zdenek Kotásek

Proceedings of the 11th IEEE Latin American Symposium on Circuits & Systems, 2020

Iterative Algorithm for Multidimensional Pareto Frontiers Intersection Determination.

Jakub Podivinsky, Ondrej Cekan, Martin Krcma, Radek Burget, Tomas Hruska, Zdenek Kotásek

Proceedings of the 11th IEEE Latin American Symposium on Circuits & Systems, 2020

Analysis of Software-Implemented Fault Tolerance: Case Study on Smart Lock.

Jakub Lojda, Richard Panek, Jakub Podivinsky, Ondrej Cekan, Martin Krcma, Zdenek Kotásek

Proceedings of the IEEE East-West Design & Test Symposium, 2020

Hardening of Smart Electronic Lock Software against Random and Deliberate Faults.

Jakub Lojda, Richard Panek, Jakub Podivinsky, Ondrej Cekan, Martin Krcma, Zdenek Kotásek

Proceedings of the 23rd Euromicro Conference on Digital System Design, 2020

Automatic Design of Reliable Systems Based on the Multiple-choice Knapsack Problem.

Jakub Lojda, Jakub Podivinsky, Ondrej Cekan, Richard Panek, Martin Krcma, Zdenek Kotásek

Proceedings of the 23rd International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2020

2019

Detecting hard synapses faults in artificial neural networks.

Martin Krcma, Zdenek Kotásek, Jakub Lojda

Proceedings of the IEEE Latin American Test Symposium, 2019

Multidimensional Pareto Frontiers Intersection Determination and Processor Optimization Case Study.

Jakub Podivinsky, Ondrej Cekan, Martin Krcma, Radek Burget, Tomas Hruska, Zdenek Kotásek

Proceedings of the 22nd Euromicro Conference on Digital System Design, 2019

Testing Reliability of Smart Electronic Locks: Analysis and the First Steps Towards.

Ondrej Cekan, Jakub Podivinsky, Jakub Lojda, Richard Panek, Martin Krcma, Zdenek Kotásek

Proceedings of the 22nd Euromicro Conference on Digital System Design, 2019

2018

A Processor Optimization Framework for a Selected Application.

Jalab Podivinsky, Ondrej Cekan, Martin Krcma, Radek Burget, Tomas Hruska, Zdenek Kotásek

Proceedings of the 2018 IEEE East-West Design & Test Symposium, 2018

2017

Functional verification based platform for evaluating fault tolerance properties.

Jakub Podivinsky, Ondrej Cekan, Jakub Lojda, Marcela Zachariásová, Martin Krcma, Zdenek Kotásek

Microprocess. Microsystems, 2017

Comparison of FPNNs models approximation capabilities and FPGA resources utilization.

Martin Krcma, Zdenek Kotásek, Jakub Lojda

Proceedings of the 13th IEEE International Conference on Intelligent Computer Communication and Processing, 2017

Data types and operations modifications: A practical approach to fault tolerance in HLS.

Jakub Lojda, Jakub Podivinsky, Zdenek Kotásek, Martin Krcma

Proceedings of the 2017 IEEE East-West Design & Test Symposium, 2017

Triple modular redundancy used in field programmable neural networks.

Martin Krcma, Zdenek Kotásek, Jakub Lojda

Proceedings of the 2017 IEEE East-West Design & Test Symposium, 2017

2016

HLS-based fault tolerance approach for SRAM-based FPGAs.

Jakub Lojda, Jakub Podivinsky, Martin Krcma, Zdenek Kotásek

Proceedings of the 2016 International Conference on Field-Programmable Technology, 2016

Implementation of fault tolerant techniques into FPNNs.

Martin Krcma, Zdenek Kotásek, Jakub Lojda

Proceedings of the 2016 International Conference on Field-Programmable Technology, 2016

2015

Fault tolerant Field Programmable Neural Networks.

Martin Krcma, Zdenek Kotásek, Jan Kastil

Proceedings of the Nordic Circuits and Systems Conference, 2015

Mapping Trained Neural Networks to FPNNs.

Martin Krcma, Jan Kastil, Zdenek Kotásek

Proceedings of the 18th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2015