Marta Ortín-Obón

Orcid: 0000-0003-3161-3793

According to our database1, Marta Ortín-Obón authored at least 14 papers between 2013 and 2018.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

Online presence:

On csauthors.net:

Bibliography

2018
On-the-Fly Power-Aware Rendering.
Comput. Graph. Forum, 2018

2017
Contrasting Laser Power Requirements of Wavelength-Routed Optical NoC Topologies Subject to the Floorplanning, Placement, and Routing Constraints of a 3-D-Stacked System.
IEEE Trans. Very Large Scale Integr. Syst., 2017

Analyzing Interfaces and Workflows for Light Field Editing.
IEEE J. Sel. Top. Signal Process., 2017

A tool for synthesizing power-efficient and custom-tailored wavelength-routed optical rings.
Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017

2016
Analysis of network-on-chip topologies for cost-efficient chip multiprocessors.
Microprocess. Microsystems, 2016

Reactive circuits: Dynamic construction of circuits for reactive traffic in homogeneous CMPs.
J. Parallel Distributed Comput., 2016

2015
Partitioning Strategies of Wavelength-Routed Optical Networks-on-Chip for Laser Power Minimization.
Proceedings of the 2015 Workshop on Exploiting Silicon Photonics for Energy-Efficient High Performance Computing, 2015

2014
Capturing the sensitivity of optical network quality metrics to its network interface parameters.
Concurr. Comput. Pract. Exp., 2014

Towards compelling cases for the viability of silicon-nanophotonic technology in future manycore systems.
Proceedings of the Eighth IEEE/ACM International Symposium on Networks-on-Chip, 2014

Augmenting manycore programmable accelerators with photonic interconnect technology for the high-end embedded computing domain.
Proceedings of the Eighth IEEE/ACM International Symposium on Networks-on-Chip, 2014

A complete electronic network interface architecture for global contention-free communication over emerging optical networks-on-chip.
Proceedings of the Great Lakes Symposium on VLSI 2014, GLSVLSI '14, Houston, TX, USA - May 21, 2014

Dynamic construction of circuits for reactive traffic in homogeneous CMPs.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

2013
Characterization and cost-efficient selection of NoC topologies for general purpose CMPs.
Proceedings of the 2013 Interconnection Network Architecture: On-Chip, Multi-Chip, 2013

Shrinking L1 Instruction Caches to Improve Energy-Delay in SMT Embedded Processors.
Proceedings of the Architecture of Computing Systems - ARCS 2013, 2013


  Loading...