Markus Winter

Affiliations:
  • Dresden University of Technology, Faculty of Computer Science


According to our database1, Markus Winter authored at least 9 papers between 2006 and 2014.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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In proceedings 
Article 
PhD thesis 
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Links

Online presence:

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Bibliography

2014
Tomahawk: Parallelism and heterogeneity in communications signal processing MPSoCs.
ACM Trans. Embed. Comput. Syst., 2014

2012
Unterstützung und Organisation von Quality-of-Service-Techniken in Kommunikationsnetzwerken auf einem Chip (Network-on-Chip).
PhD thesis, 2012

A 335Mb/s 3.9mm<sup>2</sup> 65nm CMOS flexible MIMO detection-decoding engine achieving 4G wireless data rates.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012

A source-synchronous 90Gb/s capacitively driven serial on-chip link over 6mm in 65nm CMOS.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012

2011
Fair rate packet arbitration in Network-on-Chip.
Proceedings of the IEEE 24th International SoC Conference, SOCC 2011, Taipei, Taiwan, 2011

Guaranteed service virtual channel allocation in NoCs for run-time task scheduling.
Proceedings of the Design, Automation and Test in Europe, 2011

2008
A fully programmable 40 GOPS SDR single chip baseband for LTE/WiMAX terminals.
Proceedings of the ESSCIRC 2008, 2008

A Network-on-Chip Channel Allocator for Run-Time Task Scheduling in Multi-Processor System-on-Chips.
Proceedings of the 11th Euromicro Conference on Digital System Design: Architectures, 2008

2006
Interconnection Generation for System-on-Chip Design.
Proceedings of the International Symposium on System-on-Chip, 2006


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