Markus Wedler
According to our database1,
Markus Wedler
authored at least 36 papers
between 2002 and 2015.
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Bibliography
2015
Virtual hardware-in-the-loop co-simulation for multi-domain automotive systems via the functional mock-up interface.
Proceedings of the 2015 Forum on Specification and Design Languages, 2015
2014
Proceedings of the Fifteenth International Symposium on Quality Electronic Design, 2014
2013
IPSJ Trans. Syst. LSI Des. Methodol., 2013
Compositional Completeness over reactive Constraints.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2013
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2013
A computational model for SAT-based verification of hardware-dependent low-level embedded system software.
Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013
2012
Proceedings of the Proceeding of the 2012 Forum on Specification and Design Languages, 2012
System verification of concurrent RTL modules by compositional path predicate abstraction.
Proceedings of the 49th Annual Design Automation Conference 2012, 2012
2011
STABLE: A new QF-BV SMT Solver for hard Verification Problems combining Boolean Reasoning with Computer Algebra.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2011
Formal Hardware/Software Co-Verification by Interval Property Checking with Abstraction.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2011
Formal hardware/software co-verification by interval property checking with abstraction.
Proceedings of the 48th Design Automation Conference, 2011
2010
Analyzing k-step induction to compute invariants for SAT-based property checking.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2010
Proceedings of 10th International Conference on Formal Methods in Computer-Aided Design, 2010
Complete Verification of Weakly Programmable IPs against Their Operational ISA Model.
Proceedings of the 2010 Forum on specification & Design Languages, 2010
Analyzing <i>k</i>-step induction to compute invariants for SAT-based property checking.
Proceedings of the 47th Design Automation Conference, 2010
2009
A Re-Use Methodology for SoC Protocol Compliance Verification.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2009
Proceedings of the Forum on specification and Design Languages, 2009
Proceedings of the Algorithms and Applications for Next Generation SAT Solvers, 08.11., 2009
2008
Unbounded Protocol Compliance Verification Using Interval Property Checking With Invariants.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008
Proving Functional Correctness of Weakly Programmable IPs - A Case Study with Formal Property Checking.
Proceedings of the IEEE Symposium on Application Specific Processors, 2008
Formale Verifikation einer Hardware-Implementierung des LIN-Protokoll Kontrollers.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2008
Modeling of Custom-Designed Arithmetic Components for ABL Normalization.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2008
A New Verification Technique for Custom-Designed Components at the Arithmetic Bit Level.
Proceedings of the Languages for Embedded Systems and their Applications, 2008
Proceedings of the Computer Aided Verification, 20th International Conference, 2008
Verifying full-custom multipliers by Boolean equivalence checking and an arithmetic bit level proof.
Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008
2007
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007
Arithmetic Constraints in SAT-based Property Checking.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2007
2006
A case study on applying bounded model checking to analog circuit verification.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2006
2005
Transition-by-transition FSM traversal for reachability analysis in bounded model checking.
Proceedings of the 2005 International Conference on Computer-Aided Design, 2005
Proceedings of the 42nd Design Automation Conference, 2005
2004
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004
Exploiting state encoding for invariant generation in induction-based property checking.
Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004
2003
Towards the impact of state encoding on induction-based property checking.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2003
Using RTL Statespace Information and State Encoding for Induction Based Property Checking.
Proceedings of the 2003 Design, 2003
2002
Proceedings of the 2002 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2002), 2002