Markus Olbrich

Orcid: 0000-0001-9851-5982

According to our database1, Markus Olbrich authored at least 45 papers between 1998 and 2020.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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On csauthors.net:

Bibliography

2020
Automated Model Generation Including Variations for Formal Verification of Nonlinear Analog Circuits.
Proceedings of the 18th IEEE International New Circuits and Systems Conference, 2020

Equivalence Checking Methods for Analog Circuits Using Continuous Reachable Sets.
Proceedings of the 2020 IEEE Computer Society Annual Symposium on VLSI, 2020

Extended Probability Distribution Arithmetic.
Proceedings of the 2nd IEEE International Conference on Electronics, 2020

Automatically Generated Nonlinear Analog Circuit Models Enclosing Variations with Intervals and Affine Forms for Reachability Analysis.
Proceedings of the 23rd International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2020

Establishing Reachset Conformance for the Formal Analysis of Analog Circuits.
Proceedings of the 25th Asia and South Pacific Design Automation Conference, 2020

2019
Hierarchical Verification of AMS Systems With Affine Arithmetic Decision Diagrams.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019

Enabling Complex Stimuli in Accelerated Mixed-Signal Simulation.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019

2018
STP - A Quadratic VLSI Placement Tool Using Graphic Processing Units.
Proceedings of the 17th International Symposium on Parallel and Distributed Computing, 2018

Modeling and Accelerated Mixed-Signal Simulation of a Control System.
Proceedings of the 21st IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2018

2017
Novel metrics for Analog Mixed-Signal coverage.
Proceedings of the 20th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2017

2016
Embedded tutorial: Analog-/mixed-signal verification methods for AMS coverage analysis.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

2015
Fast global interconnnect driven 3D floorplanning.
Proceedings of the 2015 IFIP/IEEE International Conference on Very Large Scale Integration, 2015

Split and merge strategies for solving uncertain equations using affine arithmetic.
Proceedings of the 8th International Conference on Simulation Tools and Techniques, 2015

Automated generation of hybrid system models for reachability analysis of nonlinear analog circuits.
Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015

2014
Robustness measurement of integrated circuits and its adaptation to aging effects.
Microelectron. Reliab., 2014

Simulation Based Verification with Range Based Signal Representations for Mixed-Signal Systems.
Proceedings of the 27th Symposium on Integrated Circuits and Systems Design, 2014

Application of Mission Profiles to enable cross-domain constraint-driven design.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

2013
Improving 3D-Floorplanning using smart selection operations in meta-heuristic optimization.
Proceedings of the 2013 IEEE International 3D Systems Integration Conference (3DIC), 2013

2012
Efficient generation of analog circuit models for accelerated mixed-signal simulation.
Proceedings of the IEEE 25th International SOC Conference, 2012

2011
A Statistical Learning Based Modeling Approach and Its Application in Leakage Library Characterization.
Proceedings of the VLSI Design 2011: 24th International Conference on VLSI Design, 2011

A gate sizing method for glitch power reduction.
Proceedings of the IEEE 24th International SoC Conference, SOCC 2011, Taipei, Taiwan, 2011

Using analog circuit behavior to generate SystemC events for an acceleration of mixed-signal simulation.
Proceedings of the IEEE 29th International Conference on Computer Design, 2011

A theoretical probabilistic simulation framework for dynamic power estimation.
Proceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design, 2011

3D floorplanning considering vertically aligned rectilinear modules using T<sup>∗</sup>-tree.
Proceedings of the 2011 IEEE International 3D Systems Integration Conference (3DIC), Osaka, Japan, January 31, 2011

2010
An Accelerated Mixed-Signal Simulation Kernel for SystemC.
Proceedings of the 2010 Forum on specification & Design Languages, 2010

Towards Abstract Analysis Techniques for Range Based System Simulations.
Proceedings of the 2010 Forum on specification & Design Languages, 2010

2009
Fast dynamic power estimation considering glitch filtering.
Proceedings of the Annual IEEE International SoC Conference, SoCC 2009, 2009

The PRAISE approach for accelerated transient analysis applied to wire models.
Proceedings of the 2009 IEEE International Behavioral Modeling and Simulation Workshop, 2009

2008
Considering possible opens in non-tree topology wire delay calculation.
Proceedings of the 18th ACM Great Lakes Symposium on VLSI 2008, 2008

Methodologies for High-Level Modelling and Evaluation in the Automotive Domain (invited).
Proceedings of the Forum on specification and Design Languages, 2008

A Trapezoidal Approach to Corner Stitching Data Structures for Arbitrary Routing Angles.
Proceedings of the 11th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2008), 2008

Distribution arithmetic for stochastical analysis.
Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008

Analog circuit simulation using range arithmetics.
Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008

2007
Robust wiring networks for DfY considering timing constraints.
Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, 2007

Range Arithmetics to Speed up Reachability Analysis of Analog Systems.
Proceedings of the Forum on specification and Design Languages, 2007

CMCal: an accurate analytical approach for the analysis of process variations with non-gaussian parameters and nonlinear functions.
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

Efficient Modeling Techniques for Dynamic Voltage Drop Analysis.
Proceedings of the 44th Design Automation Conference, 2007

2005
Routing of analog busses with parasitic symmetry.
Proceedings of the 2005 International Symposium on Physical Design, 2005

2004
Wirelength Reduction Using 3-D Physical Design.
Proceedings of the Integrated Circuit and System Design, 2004

Placement Using a Localization Probability Model (LPM).
Proceedings of the 2004 Design, 2004

2003
Substrate Modeling and Noise Reduction in Mixed-Signal Circuits.
Proceedings of the IFIP VLSI-SoC 2003, 2003

Placing substrate contacts into mixed-signal circuits controlling circuit performance.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2003

2001
An improved hierarchical classification algorithm for structural analysis of integrated circuits.
Proceedings of the Conference on Design, Automation and Test in Europe, 2001

1998
Relationenorientiertes Modellieren mit Objekten in der Bauinformatik.
PhD thesis, 1998

An Optimized Design Flow for Fast FPGA-Based Rapid Prototyping.
Proceedings of the Field-Programmable Logic and Applications, 1998


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