Markus Karner

According to our database1, Markus Karner authored at least 14 papers between 2005 and 2024.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2024

TCAD for Circuits and Systems: Process Emulation, Parasitics Extraction, Self-Heating.
Proceedings of the IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium, 2024

2023
A Study of the Variability and Design Considerations of Ferroelectric VNAND Memories With Polycrystalline Films Using An Experimentally Validated TCAD Model.
Proceedings of the 53rd IEEE European Solid-State Device Research Conference, 2023

2022
nnU-Net Pre- and Postprocessing Strategies for UW-OCTA Segmentation Tasks in Diabetic Retinopathy Analysis.
Proceedings of the Mitosis Domain Generalization and Diabetic Retinopathy Analysis, 2022

A Novel Approach to Modeling Insulator Wave-Function Penetration and Interface Roughness Scattering in MOSFETs.
Proceedings of the 52nd IEEE European Solid-State Device Research Conference, 2022

2021
Reliability and Variability-Aware DTCO Flow: Demonstration of Projections to N3 FinFET and Nanosheet Technologies.
Proceedings of the IEEE International Reliability Physics Symposium, 2021

A TCAD Compatible SONOS Trapping Layer Model for Accurate Programming Dynamics.
Proceedings of the IEEE International Memory Workshop, 2021

1.5-nm Node Surrounding Gate Transistor (SGT)-SRAM Cell with Staggered Pillar and Self-Aligned Process for Gate, Bottom Contact, and Pillar.
Proceedings of the IEEE International Memory Workshop, 2021

2018
Cell Designer - a Comprehensive TCAD-Based Framework for DTCO of Standard Logic Cells.
Proceedings of the 48th European Solid-State Device Research Conference, 2018

2015
Predictive physical simulation of III/V quantum-well MISFETs for logic applications.
Proceedings of the 45th European Solid State Device Research Conference, 2015

2010
Interface traps density-of-states as a vital component for hot-carrier degradation modeling.
Microelectron. Reliab., 2010

2007
VSP - A gate stack analyzer.
Microelectron. Reliab., 2007

Comparison of deposition models for a TEOS LPCVD process.
Microelectron. Reliab., 2007

2005
Efficient Calculation of Quasi-bound States for the Simulation of Direct Tunneling.
Proceedings of the Large-Scale Scientific Computing, 5th International Conference, 2005


  Loading...