Markus Fritscher

Orcid: 0000-0003-2754-7287

According to our database1, Markus Fritscher authored at least 14 papers between 2019 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2024
Cycle-Accurate FPGA Emulation of RRAM Crossbar Array: Efficient Device and Variability Modeling with Energy Consumption Assessment.
Proceedings of the 25th IEEE Latin American Test Symposium, 2024

From Device to Application - Integrating RRAM Accelerator Blocks into Large AI Systems.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2024

Area-Efficient Digital Design Using RRAM-CMOS Standard Cells.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2024

Towards Reliable and Energy-Efficient RRAM Based Discrete Fourier Transform Accelerator.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2024

Comparison of a Binary Signed-Digit Adder with Conventional Binary Adder Circuits on Layout Level.
Proceedings of the Architecture of Computing Systems - 37th International Conference, 2024

2023
An RRAM-based building block for reprogrammable non-uniform sampling ADCs.
it Inf. Technol., May, 2023

Prototyping Reconfigurable RRAM-Based AI Accelerators Using the RISC-V Ecosystem and Digital Twins.
Proceedings of the High Performance Computing, 2023

One-Transistor-Multiple-RRAM Cells for Energy-Efficient In-Memory Computing.
Proceedings of the 21st IEEE Interregional NEWCAS Conference, 2023

Technology-Aware Drift Resilience Analysis of RRAM Crossbar Array Configurations.
Proceedings of the 21st IEEE Interregional NEWCAS Conference, 2023

2022
Accelerating Veins Simulations by Utilizing Task Parallelism on a HPC Cluster without Introducing Major Inaccuracies.
Proceedings of the 13th International Symposium on Communication Systems, 2022

2021
Mitigating the Effects of RRAM Process Variation on the Accuracy of Artificial Neural Networks.
Proceedings of the Embedded Computer Systems: Architectures, Modeling, and Simulation, 2021

Simulating large neural networks embedding MLC RRAM as weight storage considering device variations.
Proceedings of the 12th IEEE Latin America Symposium on Circuits and System, 2021

2020
A Model-to-Circuit Compiler for Evaluation of DNN Accelerators based on Systolic Arrays and Multibit Emerging Memories.
Proceedings of the 9th International Conference on Modern Circuits and Systems Technologies, 2020

2019
Simulating Memristive Systems in Mixed-Signal Mode using Commercial Design Tools.
Proceedings of the 26th IEEE International Conference on Electronics, Circuits and Systems, 2019


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