Marko S. Andjelkovic
Orcid: 0000-0001-6419-2062
According to our database1,
Marko S. Andjelkovic
authored at least 48 papers
between 2015 and 2024.
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Bibliography
2024
FPGA Implementation of a Fault-Tolerant Fused and Branched CNN Accelerator With Reconfigurable Capabilities.
IEEE Access, 2024
IEEE Access, 2024
Radiation-Hardening-by-Design Triple Modular Redundancy Flip-Flop with Self-Correction.
Proceedings of the 2024 IEEE Nordic Circuits and Systems Conference (NorCAS), 2024
Silicon Lifecycle Management Based on On-Chip Cross-Layer Sensing and Analytics for Space Applications.
Proceedings of the 25th IEEE Latin American Test Symposium, 2024
Aging and Soft Error Resilience in Reconfigurable CNN Accelerators Employing a Multi-Purpose On-Chip Sensor.
Proceedings of the 25th IEEE Latin American Test Symposium, 2024
Space Radiation Flux Driven Fault Injection for Evaluating Dynamic Mitigation Strategies.
Proceedings of the 25th IEEE Latin American Test Symposium, 2024
Simulation-Based Analysis and Modeling of Generated Single Event Transient Pulse Width.
Proceedings of the 25th IEEE Latin American Test Symposium, 2024
A Holistic Approach for Characterization of SET Effects in a Standard Digital Cell Library.
Proceedings of the 15th IEEE Latin America Symposium on Circuits and Systems, 2024
Proceedings of the 27th Euromicro Conference on Digital System Design, 2024
2023
IEEE Trans. Circuits Syst. II Express Briefs, March, 2023
Proceedings of the IEEE Nordic Circuits and Systems Conference, 2023
Proceedings of the 26th Euromicro Conference on Digital System Design, 2023
Towards a Comprehensive SET Analysis Flow for VLSI Circuits using Static Timing Analysis.
Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2023
Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2023
Proceedings of the 38th Conference on Design of Circuits and Integrated Systems, 2023
2022
Response of Commercial P-Channel Power VDMOS Transistors to Ionizing Irradiation and Bias Temperature Stress.
J. Circuits Syst. Comput., December, 2022
Analysis of Single Event Transient Effects in Standard Delay Cells Based on Decoupling Capacitors.
J. Circuits Syst. Comput., December, 2022
A design concept for radiation hardened RADFET readout system for space applications.
Microprocess. Microsystems, April, 2022
A methodology for characterization, modeling and mitigation of single event transient effects in CMOS standard combinational cells (Eine Methode zur Charakterisierung, Modellierung und Minderung von SET Effekten in kombinierten CMOS-Standardzellen)
PhD thesis, 2022
Solar Particle Event and Single Event Upset Prediction from SRAM-Based Monitor and Supervised Machine Learning.
IEEE Trans. Emerg. Top. Comput., 2022
Fast Error Propagation Probability Estimates by Answer Set Programming and Approximate Model Counting.
IEEE Access, 2022
2021
IEEE Trans. Circuits Syst. I Regul. Pap., 2021
CoRR, 2021
Proceedings of the 12th IEEE Latin America Symposium on Circuits and System, 2021
A Tunable Single Event Transient Filter Based on Digitally Controlled Capacitive Delay Cells.
Proceedings of the 36th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2021
2020
Microelectron. J., 2020
Proceedings of the 26th IEEE International Symposium on On-Line Testing and Robust System Design, 2020
Proceedings of the 27th IEEE International Conference on Electronics, Circuits and Systems, 2020
Proceedings of the IEEE East-West Design & Test Symposium, 2020
Proceedings of the 23rd Euromicro Conference on Digital System Design, 2020
Proceedings of the 23rd Euromicro Conference on Digital System Design, 2020
Hardware Accelerator Design with Supervised Machine Learning for Solar Particle Event Prediction.
Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2020
2019
Characterization and Modeling of SET Generation Effects in CMOS Standard Logic Cells.
Proceedings of the 25th IEEE International Symposium on On-Line Testing and Robust System Design, 2019
Proceedings of the 26th IEEE International Conference on Electronics, Circuits and Systems, 2019
Proceedings of the 22nd Euromicro Conference on Digital System Design, 2019
2018
Microelectron. Reliab., 2018
Proceedings of the 25th IEEE International Conference on Electronics, Circuits and Systems, 2018
Impact of Resistive Open and Bridge Defects on the SET Robustness of Standard CMOS Combinational Logic.
Proceedings of the 2018 IEEE East-West Design & Test Symposium, 2018
D-SET Mitigation Using Common Clock Tree Insertion Techniques for Triple-Clock TMR Flip-Flop.
Proceedings of the 21st Euromicro Conference on Digital System Design, 2018
Flip-Flop SEUs Mitigation through Partial Hardening of Internal Latch and Adjustment of Clock Duty Cycle.
Proceedings of the 21st IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2018
2017
Proceedings of the 23rd IEEE International Symposium on On-Line Testing and Robust System Design, 2017
Proceedings of the Euromicro Conference on Digital System Design, 2017
Proceedings of the 20th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2017
A Critical Charge Model for Estimating the SET and SEU Sensitivity: A Muller C-Element Case Study.
Proceedings of the 26th IEEE Asian Test Symposium, 2017
2016
Proceedings of the 22nd IEEE International Symposium on On-Line Testing and Robust System Design, 2016
2015
Circuit-Level Simulation of the Single Event Transients in an On-Chip Single Event Latchup Protection Switch.
J. Electron. Test., 2015
Simulation-Based Analysis of the Single Event Transient Response of a Single Event Latchup Protection Switch.
Proceedings of the 18th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2015