Mark Spaeth
According to our database1,
Mark Spaeth
authored at least 2 papers
between 2007 and 2012.
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Bibliography
2012
A 32-core RISC microprocessor with network accelerators, power management and testability features.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012
2007
A 14-b 30MS/s 0.75mm<sup>2</sup> Pipelined ADC with On-Chip Digital Self-Calibration.
Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, 2007