Mark Neidengard

According to our database, Mark Neidengard authored at least 5 papers between 2009 and 2021.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2021

29.3 80ns Fast-Lock 0.4-to-6.5GHz Clock Generator with Self- Referenced Asynchronous Adaptive Droop Mitigation.

Praveen Mosalikanti, Qi Wang, Kuan-Yueh James Shen, Mark Neidengard, Syed Feruz Syed Farooq, Vaughn Grossnickle, Nasser A. Kurd

Proceedings of the IEEE International Solid-State Circuits Conference, 2021

2018

A Flexible, Low-Power Analog PLL for SoC and Processors in 14nm CMOS.

Kuan-Yueh James Shen, Syed Feruz Syed Farooq, Yongping Fan, Khoa Minh Nguyen, Qi Wang, Mark Neidengard, Nasser A. Kurd, Amr Elshazly

IEEE Trans. Circuits Syst. I Regul. Pap., 2018

2015

Haswell: A Family of IA 22 nm Processors.

Nasser A. Kurd, Muntaquim Chowdhury, Edward Burton, Thomas P. Thomas, Christopher Mozak, Brent Boswell, Praveen Mosalikanti, Mark Neidengard, Anant Deval, Ashish Khanna, Nasirul Chowdhury, Ravi Rajwar, Timothy M. Wilson, Rajesh Kumar

IEEE J. Solid State Circuits, 2015

2011

A Family of 32 nm IA Processors.

Nasser A. Kurd, Subramani Bhamidipati, Christopher Mozak, Jeffrey L. Miller, Praveen Mosalikanti, Timothy M. Wilson, Ali M. El-Husseini, Mark Neidengard, Ramy E. Aly, Mahadev Nemani, Muntaquim Chowdhury, Rajesh Kumar

IEEE J. Solid State Circuits, 2011

2009

Next Generation Intel¯ Core™ Micro-Architecture (Nehalem) Clocking.

Nasser A. Kurd, Praveen Mosalikanti, Mark Neidengard, Jonathan Douglas, Rajesh Kumar

IEEE J. Solid State Circuits, 2009