Mark M. Tehranipoor

According to our database, Mark M. Tehranipoor authored at least 416 papers between 2005 and 2024.

Collaborative distances:

• Dijkstra number of three.
• Erdős number of three.

2024

VLSI Test and Trust Roundtable.

Ramesh Karri, Janusz Rajski, Rob Aitken, Subhasish Mitra, Mark M. Tehranipoor

IEEE Des. Test, December, 2024

The Road Not Taken: eFPGA Accelerators Utilized for SoC Security Auditing.

Mridha Md Mashahedur Rahman, Shams Tarek, Kimia Zamiri Azar, Mark M. Tehranipoor, Farimah Farahmandi

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., October, 2024

Automatic Asset Identification for Assertion-Based SoC Security Verification.

Avinash Ayalasomayajula, Nusrat Farzana Dipu, Mark M. Tehranipoor, Farimah Farahmandi

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., October, 2024

Efficient SoC Security Monitoring: Quality Attributes and Potential Solutions.

Mridha Md Mashahedur Rahman, Shams Tarek, Kimia Zamiri Azar, Mark M. Tehranipoor, Farimah Farahmandi

IEEE Des. Test, August, 2024

Fuzzing for Automated SoC Security Verification: Challenges and Solution.

Muhammad Monir Hossain, Kimia Zamiri Azar, Fahim Rahman, Farimah Farahmandi, Mark M. Tehranipoor

IEEE Des. Test, August, 2024

FTC: A Universal Framework for Fault-Injection Attack Detection and Prevention.

Md Rafid Muttaki, Md Habibur Rahman, Akshay Kulkarni, Mark M. Tehranipoor, Farimah Farahmandi

IEEE Trans. Very Large Scale Integr. Syst., July, 2024

FLAT: Layout-Aware and Security Property-Assisted Timing Fault-Injection Attack Assessment.

Amit Mazumder Shuvo, Tao Zhang, Farimah Farahmandi, Mark M. Tehranipoor

IEEE Trans. Very Large Scale Integr. Syst., June, 2024

TrustGuard: Standalone FPGA-Based Security Monitoring Through Power Side-Channel.

Tao Zhang, Mark M. Tehranipoor, Farimah Farahmandi

IEEE Trans. Very Large Scale Integr. Syst., February, 2024

Heterogeneous Integration Supply Chain Integrity Through Blockchain and CHSM.

Paul Calzada, Md Sami Ul Islam Sami, Kimia Zamiri Azar, Fahim Rahman, Farimah Farahmandi, Mark M. Tehranipoor

ACM Trans. Design Autom. Electr. Syst., January, 2024

Exploring the Abyss? Unveiling Systems-on-Chip Hardware Vulnerabilities Beneath Software.

Sree Ranjani Rajendran, Nusrat Farzana Dipu, Shams Tarek, Hadi Mardani Kamali, Farimah Farahmandi, Mark M. Tehranipoor

IEEE Trans. Inf. Forensics Secur., 2024

AGILE: Automated Assertion Generation to Detect Information Leakage Vulnerabilities.

Nusrat Farzana Dipu, Avinash Ayalasomayajula, Mark M. Tehranipoor, Farimah Farahmandi

IEEE Trans. Inf. Forensics Secur., 2024

Improving Bounded Model Checkers Scalability for Circuit De-Obfuscation: An Exploration.

Kimia Zamiri Azar, Hadi Mardani Kamali, Farimah Farahmandi, Mark M. Tehranipoor

IEEE Trans. Inf. Forensics Secur., 2024

INSPECT: Investigating Supply Chain and Cyber-Physical Security of Battery Systems.

Tao Zhang, Shang Shi, Md Habibur Rahman, Nitin Varshney, Akshay Kulkarni, Farimah Farahmandi, Mark M. Tehranipoor

IACR Cryptol. ePrint Arch., 2024

SoCureLLM: An LLM-driven Approach for Large-Scale System-on-Chip Security Verification and Policy Generation.

Shams Tarek, Dipayan Saha, Sujan Kumar Saha, Mark M. Tehranipoor, Farimah Farahmandi

IACR Cryptol. ePrint Arch., 2024

A Survey on SoC Security Verification Methods at the Pre-silicon Stage.

Rasheed Kibria, Farimah Farahmandi, Mark M. Tehranipoor

IACR Cryptol. ePrint Arch., 2024

Advancing Trustworthiness in System-in-Package: A Novel Root-of-Trust Hardware Security Module for Heterogeneous Integration.

Md Sami Ul Islam Sami, Tao Zhang, Amit Mazumder Shuvo, Md. Saad Ul Haque, Paul Calzada, Kimia Zamiri Azar, Hadi Mardani Kamali, Fahim Rahman, Farimah Farahmandi, Mark M. Tehranipoor

IEEE Access, 2024

LLM for SoC Security: A Paradigm Shift.

Dipayan Saha, Shams Tarek, Katayoon Yahyaei, Sujan Kumar Saha, Jingbo Zhou, Mark M. Tehranipoor, Farimah Farahmandi

IEEE Access, 2024

CAD Tools Pathway in Hardware Security.

Sree Ranjani Rajendran, Farimah Farahmandi, Mark M. Tehranipoor

Proceedings of the 37th International Conference on VLSI Design and 23rd International Conference on Embedded Systems, 2024

HI-SST: Safeguarding SiP Authenticity Through Secure Split-Test in Heterogeneous Integration.

Paul Calzada, Md Sami Ul Islam Sami, Jingbo Zhou, Kimia Zamiri Azar, Farimah Farahmandi, Mark M. Tehranipoor

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2024

SAP: Silicon Authentication Platform for System-on-Chip Supply Chain Vulnerabilities.

Md Sami Ul Islam Sami, Jingbo Zhou, Sujan Kumar Saha, Fahim Rahman, Farimah Farahmandi, Mark M. Tehranipoor

Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2024

Empowering Hardware Security with LLM: The Development of a Vulnerable Hardware Database.

Dipayan Saha, Katayoon Yahyaei, Sujan Kumar Saha, Mark M. Tehranipoor, Farimah Farahmandi

Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust, 2024

Photon Emission Modeling and Machine-Learning Assisted Pre-Silicon Optical Side-Channel Simulation.

Henian Li, Lang Lin, Norman Chang, Sreeja Chowdhury, Dylan Mcguire, Bozidar Novakovic, Kazuki Monta, Makoto Nagata, Ying-Shiun Li, Pramod M. S, Piin-Chen Yeh, Jyh-Shing Roger Jang, Chengjie Xi, Qiutong Jin, Navid Asadi, Mark M. Tehranipoor

Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust, 2024

SeeMLess: Security Evaluation of Logic Locking using Machine Learning oriented Estimation.

Bulbul Ahmed, M. Sazadur Rahman, Kimia Zamiri Azar, Farimah Farahmandi, Fahim Rahman, Mark M. Tehranipoor

Proceedings of the Great Lakes Symposium on VLSI 2024, 2024

RL-TPG: Automated Pre-Silicon Security Verification through Reinforcement Learning-Based Test Pattern Generation.

Nurun Nahar Mondol, Arash Vafaei, Kimia Zamiri Azar, Farimah Farahmandi, Mark M. Tehranipoor

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2024

GATE-SiP: Enabling Authenticated Encryption Testing in Systems-in-Package.

Galib Ibne Haidar, Kimia Zamiri Azar, Hadi Mardani Kamali, Mark M. Tehranipoor, Farimah Farahmandi

Proceedings of the 61st ACM/IEEE Design Automation Conference, 2024

FormalFuzzer: Formal Verification Assisted Fuzz Testing for SoC Vulnerability Detection.

Nusrat Farzana Dipu, Muhammad Monir Hossain, Kimia Zamiri Azar, Farimah Farahmandi, Mark M. Tehranipoor

Proceedings of the 29th Asia and South Pacific Design Automation Conference, 2024

2023

iPROBE: Internal Shielding Approach for Protecting Against Front-Side and Back-Side Probing Attacks.

Minyan Gao, M. Sazadur Rahman, Nitin Varshney, Mark M. Tehranipoor, Domenic Forte

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., December, 2023

FSMx-Ultra: Finite State Machine Extraction From Gate-Level Netlist for Security Assessment.

Rasheed Kibria, Farimah Farahmandi, Mark M. Tehranipoor

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., November, 2023

Enabling Security of Heterogeneous Integration: From Supply Chain to In-Field Operations.

Md Sami Ul Islam Sami, Hadi Mardani Kamali, Farimah Farahmandi, Fahim Rahman, Mark M. Tehranipoor

IEEE Des. Test, October, 2023

HLock+: A Robust and Low-Overhead Logic Locking at the High-Level Language.

Md Rafid Muttaki, Roshanak Mohammadivojdan, Hadi Mardani Kamali, Mark M. Tehranipoor, Farimah Farahmandi

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., July, 2023

FPIC: A Novel Semantic Dataset for Optical PCB Assurance.

Nathan Jessurun, Olivia P. Dizon-Paradis, Jacob Harrison, Shajib Ghosh, Mark M. Tehranipoor, Damon L. Woodard, Navid Asadizanjani

ACM J. Emerg. Technol. Comput. Syst., April, 2023

FPGA-Chain: Enabling Holistic Protection of FPGA Supply Chain With Blockchain Technology.

Tao Zhang, Fahim Rahman, Mark M. Tehranipoor, Farimah Farahmandi

IEEE Des. Test, April, 2023

Introduction to the Special Issue on CAD for Security: Pre-silicon Security Sign-off Solutions Through Design Cycle.

Farimah Farahmandi, Ankur Srivastava, Giorgio Di Natale, Mark M. Tehranipoor

ACM J. Emerg. Technol. Comput. Syst., January, 2023

A Comprehensive Survey on Non-Invasive Fault Injection Attacks.

Amit Mazumder Shuvo, Tao Zhang, Farimah Farahmandi, Mark M. Tehranipoor

IACR Cryptol. ePrint Arch., 2023

ARC-FSM-G: Automatic Security Rule Checking for Finite State Machine at the Netlist Abstraction.

Rasheed Kibria, Farimah Farahmandi, Mark M. Tehranipoor

IACR Cryptol. ePrint Arch., 2023

ReTrustFSM: Toward RTL Hardware Obfuscation-A Hybrid FSM Approach.

M. Sazadur Rahman, Rui Guo, Hadi Mardani Kamali, Fahim Rahman, Farimah Farahmandi, Mark M. Tehranipoor

IEEE Access, 2023

CAPEC: A Cellular Automata Guided FSM-based IP Authentication Scheme.

Mridha Md Mashahedur Rahman, M. Sazadur Rahman, Rasheed Kibria, Mike Borza, Bandy Reddy, Adam Cron, Fahim Rahman, Mark M. Tehranipoor, Farimah Farahmandi

Proceedings of the 41st IEEE VLSI Test Symposium, 2023

Special Session: CAD for Hardware Security - Promising Directions for Automation of Security Assurance.

Sohrab Aftabjahani, Mark M. Tehranipoor, Farimah Farahmandi, Bulbul Ahmed, Ryan Kastner, Francesco Restuccia, Andres Meza, Kaki Ryan, Nicole Fern, Jasper Van Woudenberg, Rajesh Velegalati, Cees-Bart Breunesse, Cynthia Sturton, Calvin Deutschbein

Proceedings of the 41st IEEE VLSI Test Symposium, 2023

TaintFuzzer: SoC Security Verification using Taint Inference-enabled Fuzzing.

Muhammad Monir Hossain, Nusrat Farzana Dipu, Kimia Zamiri Azar, Fahim Rahman, Farimah Farahmandi, Mark M. Tehranipoor

Proceedings of the IEEE/ACM International Conference on Computer Aided Design, 2023

Towards Secure Classical-Quantum Systems.

Daniel Volya, Tao Zhang, Nashmin Alam, Mark M. Tehranipoor, Prabhat Mishra

Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust, 2023

Dual Channel EM/Power Attack Using Mutual Information and its Real-time Implementation.

Yunkai Bai, Jungmin Park, Mark M. Tehranipoor, Domenic Forte

Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust, 2023

Microelectronics Security in CHIPS Era.

Mark M. Tehranipoor

Proceedings of the Great Lakes Symposium on VLSI 2023, 2023

BitFREE: On Significant Speedup and Security Applications of FPGA Bitstream Format Reverse Engineering.

Tao Zhang, Mark M. Tehranipoor, Farimah Farahmandi

Proceedings of the IEEE European Test Symposium, 2023

PSC-Watermark: Power Side Channel Based IP Watermarking Using Clock Gates.

Upoma Das, M. Sazadur Rahman, N. Nalla Anandakumar, Kimia Zamiri Azar, Fahim Rahman, Mark M. Tehranipoor, Farimah Farahmandi

Proceedings of the IEEE European Test Symposium, 2023

QuardTropy: Detecting and Quantifying Unauthorized Information Leakage in Hardware Designs using g-entropy.

Hasan Al Shaikh, Mohammad Bin Monjil, Kimia Zamiri Azar, Farimah Farahmandi, Mark M. Tehranipoor, Fahim Rahman

Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2023

HUnTer: Hardware Underneath Trigger for Exploiting SoC-level Vulnerabilities.

Sree Ranjani Rajendran, Shams Tarek, Benjamin M. Hicks, Hadi Mardani Kamali, Farimah Farahmandi, Mark M. Tehranipoor

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

RTLock: IP Protection using Scan-Aware Logic Locking at RTL.

Md Rafid Muttaki, Shyvagata Saha, Hadi Mardani Kamali, Fahim Rahman, Mark M. Tehranipoor, Farimah Farahmandi

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

SheLL: Shrinking eFPGA Fabrics for Logic Locking.

Hadi Mardani Kamali, Kimia Zamiri Azar, Farimah Farahmandi, Mark M. Tehranipoor

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

SoCFuzzer: SoC Vulnerability Detection using Cost Function enabled Fuzz Testing.

Muhammad Monir Hossain, Arash Vafaei, Kimia Zamiri Azar, Fahim Rahman, Farimah Farahmandi, Mark M. Tehranipoor

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

EvoLUTe: Evaluation of Look-Up-Table-based Fine-Grained IP Redaction.

Rui Guo, M. Sazadur Rahman, Hadi Mardani Kamali, Fahim Rahman, Farimah Farahmandi, Mark M. Tehranipoor

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

ActiWate: Adaptive and Design-agnostic Active Watermarking for IP Ownership in Modern SoCs.

Zahin Ibnat, M. Sazadur Rahman, Mridha Md Mashahedur Rahman, Hadi Mardani Kamali, Mark M. Tehranipoor, Farimah Farahmandi

Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023

SecHLS: Enabling Security Awareness in High-Level Synthesis.

Shang Shi, Nitin Pundir, Hadi Mardani Kamali, Mark M. Tehranipoor, Farimah Farahmandi

Proceedings of the 28th Asia and South Pacific Design Automation Conference, 2023

SHarPen: SoC Security Verification by Hardware Penetration Test.

Hasan Al Shaikh, Arash Vafaei, Mridha Md Mashahedur Rahman, Kimia Zamiri Azar, Fahim Rahman, Farimah Farahmandi, Mark M. Tehranipoor

Proceedings of the 28th Asia and South Pacific Design Automation Conference, 2023

2022

Trust-Hub Trojan Benchmark for Hardware Trojan Detection Model Creation using Machine Learning.

Hassan Salmani, Mark M. Tehranipoor, Sarwono Sutikno, Fajar Wijitrisnanto

Dataset, September, 2022

Power Side-Channel Leakage Assessment Framework at Register-Transfer Level.

Nitin Pundir, Jungmin Park, Farimah Farahmandi, Mark M. Tehranipoor

IEEE Trans. Very Large Scale Integr. Syst., 2022

RASCv2: Enabling Remote Access to Side-Channels for Mission Critical and IoT Systems.

Yunkai Bai, Andrew Stern, Jungmin Park, Mark M. Tehranipoor, Domenic Forte

ACM Trans. Design Autom. Electr. Syst., 2022

eChain: A Blockchain-Enabled Ecosystem for Electronic Device Authenticity Verification.

Nidish Vashistha, Muhammad Monir Hossain, Md Rakib Shahriar, Farimah Farahmandi, Fahim Rahman, Mark M. Tehranipoor

IEEE Trans. Consumer Electron., 2022

SoFI: Security Property-Driven Vulnerability Assessments of ICs Against Fault-Injection Attacks.

Huanyu Wang, Henian Li, Fahim Rahman, Mark M. Tehranipoor, Farimah Farahmandi

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

Detecting Hardware Trojans Using Combined Self-Testing and Imaging.

Nidish Vashistha, Hangwei Lu, Qihang Shi, Damon L. Woodard, Navid Asadizanjani, Mark M. Tehranipoor

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

ACED-IT: Assuring Confidential Electronic Design Against Insider Threats in a Zero-Trust Environment.

Andrew Stern, Huanyu Wang, Fahim Rahman, Farimah Farahmandi, Mark M. Tehranipoor

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

Analyzing Security Vulnerabilities Induced by High-level Synthesis.

Nitin Pundir, Sohrab Aftabjahani, Rosario Cammarota, Mark M. Tehranipoor, Farimah Farahmandi

ACM J. Emerg. Technol. Comput. Syst., 2022

ToSHI - Towards Secure Heterogeneous Integration: Security Risks, Threat Assessment, and Assurance.

Nidish Vashistha, Md Latifur Rahman, Md. Saad Ul Haque, Azim Uddin, Md Sami Ul Islam Sami, Amit Mazumder Shuo, Paul Calzada, Farimah Farahmandi, Navid Asadizanjani, Fahim Rahman, Mark M. Tehranipoor

IACR Cryptol. ePrint Arch., 2022

Digital Twin for Secure Semiconductor Lifecycle Management: Prospects and Applications.

Hasan Al Shaikh, Mohammad Bin Monjil, Shigang Chen, Farimah Farahmandi, Navid Asadizanjani, Mark M. Tehranipoor, Fahim Rahman

IACR Cryptol. ePrint Arch., 2022

PQC-SEP: Power Side-channel Evaluation Platform for Post-Quantum Cryptography Algorithms.

Jungmin Park, N. Nalla Anandakumar, Dipayan Saha, Dhwani Mehta, Nitin Pundir, Fahim Rahman, Farimah Farahmandi, Mark M. Tehranipoor

IACR Cryptol. ePrint Arch., 2022

FICS PCB X-ray: A dataset for automated printed circuit board inter-layers inspection.

Dhwani Mehta, John True, Olivia P. Dizon-Paradis, Nathan Jessurun, Damon L. Woodard, Navid Asadizanjani, Mark M. Tehranipoor

IACR Cryptol. ePrint Arch., 2022

Advances in Logic Locking: Past, Present, and Prospects.

Hadi Mardani Kamali, Kimia Zamiri Azar, Farimah Farahmandi, Mark M. Tehranipoor

IACR Cryptol. ePrint Arch., 2022

Secure Physical Design.

Sukanta Dey, Jungmin Park, Nitin Pundir, Dipayan Saha, Amit Mazumder Shuvo, Dhwani Mehta, Navid Asadi, Fahim Rahman, Farimah Farahmandi, Mark M. Tehranipoor

IACR Cryptol. ePrint Arch., 2022

Fuzz, Penetration, and AI Testing for SoC Security Verification: Challenges and Solutions.

Kimia Zamiri Azar, Muhammad Monir Hossain, Arash Vafaei, Hasan Al Shaikh, Nurun N. Mondol, Fahim Rahman, Mark M. Tehranipoor, Farimah Farahmandi

IACR Cryptol. ePrint Arch., 2022

Rethinking Watermark: Providing Proof of IP Ownership in Modern SoCs.

N. Nalla Anandakumar, M. Sazadur Rahman, Mridha Md Mashahedur Rahman, Rasheed Kibria, Upoma Das, Farimah Farahmandi, Fahim Rahman, Mark M. Tehranipoor

IACR Cryptol. ePrint Arch., 2022

Secure Interposer-Based Heterogeneous Integration.

M. Shafkat M. Khan, Chengjie Xi, Aslam A. Khan, M. Tanjidur Rahman, Mark M. Tehranipoor, Navid Asadizanjani

IEEE Des. Test, 2022

EM Side Channels in Hardware Security: Attacks and Defenses.

Jiaji He, Xiaolong Guo, Mark M. Tehranipoor, Apostol Vassilev, Yier Jin

IEEE Des. Test, 2022

On Backside Probing Techniques and Their Emerging Security Threats.

Liton Kumar Biswas, Leonidas Lavdas, M. Tanjidur Rahman, Mark M. Tehranipoor, Navid Asadizanjani

IEEE Des. Test, 2022

Real-time instruction-level verification of remote IoT/CPS devices via side channels.

Yunkai Bai, Jungmin Park, Mark M. Tehranipoor, Domenic Forte

Discov. Internet Things, 2022

FSMx: Finite State Machine Extraction from Flattened Netlist With Application to Security.

Rasheed Kibria, Nusrat Farzana, Farimah Farahmandi, Mark M. Tehranipoor

Proceedings of the 40th IEEE VLSI Test Symposium, 2022

RTL-FSMx: Fast and Accurate Finite State Machine Extraction at the RTL for Security Applications.

Rasheed Kibria, M. Sazadur Rahman, Farimah Farahmandi, Mark M. Tehranipoor

Proceedings of the IEEE International Test Conference, 2022

ADWIL: A Zero-Overhead Analog Device Watermarking Using Inherent IP Features.

Upoma Das, Md Rafid Muttaki, Mark M. Tehranipoor, Farimah Farahmandi

Proceedings of the IEEE International Test Conference, 2022

LDTFI: Layout-aware Timing Fault-Injection Attack Assessment Against Differential Fault Analysis.

Amit Mazumder Shuvo, Nitin Pundir, Jungmin Park, Farimah Farahmandi, Mark M. Tehranipoor

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2022

Security Properties Driven Pre-Silicon Laser Fault Injection Assessment.

Nitin Pundir, Henian Li, Lang Lin, Norman Chang, Farimah Farahmandi, Mark M. Tehranipoor

Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust, 2022

FTC: A Universal Sensor for Fault Injection Attack Detection.

Md Rafid Muttaki, Tao Zhang, Mark M. Tehranipoor, Farimah Farahmandi

Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust, 2022

Warm Up before Circuit De-obfuscation? An Exploration through Bounded-Model-Checkers.

Kimia Zamiri Azar, Hadi Mardani Kamali, Farimah Farahmandi, Mark M. Tehranipoor

Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust, 2022

AIME: Watermarking AI Models by Leveraging Errors.

Dhwani Mehta, Nurun N. Mondol, Farimah Farahmandi, Mark M. Tehranipoor

Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022

O'clock: lock the clock via clock-gating for SoC IP protection.

M. Sazadur Rahman, Rui Guo, Hadi Mardani Kamali, Fahim Rahman, Farimah Farahmandi, Mohamed Abdel-Moneum, Mark M. Tehranipoor

Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022

2021

Security Assessment of Dynamically Obfuscated Scan Chain Against Oracle-guided Attacks.

M. Sazadur Rahman, Adib Nahiyan, Fahim Rahman, Saverio Fazzari, Kenneth Plaks, Farimah Farahmandi, Domenic Forte, Mark M. Tehranipoor

ACM Trans. Design Autom. Electr. Syst., 2021

A Metal-Via Resistance Based Physically Unclonable Function With Backend Incremental ADC.

Beomsoo Park, Domenic Forte, Mark M. Tehranipoor, Nima Maghari

IEEE Trans. Circuits Syst. I Regul. Pap., 2021

CONCEALING-Gate: Optical Contactless Probing Resilient Design.

M. Tanjidur Rahman, Nusrat Farzana, Dhwani Mehta, Shahin Tajik, Mark M. Tehranipoor, Navid Asadizanjani

ACM J. Emerg. Technol. Comput. Syst., 2021

Hardware Trust and Assurance through Reverse Engineering: A Tutorial and Outlook from Image Analysis and Machine Learning Perspectives.

Ulbert J. Botero, Ronald Wilson, Hangwei Lu, Mir Tanjidur Rahman, Mukhil A. Mallaiyan, Fatemeh Ganji, Navid Asadizanjani, Mark M. Tehranipoor, Damon L. Woodard, Domenic Forte

ACM J. Emerg. Technol. Comput. Syst., 2021

Rock'n'roll PUFs: crafting provably secure pufs from less secure ones (extended version).

Fatemeh Ganji, Shahin Tajik, Pascal Stauss, Jean-Pierre Seifert, Mark M. Tehranipoor, Domenic Forte

J. Cryptogr. Eng., 2021

On malicious implants in PCBs throughout the supply chain.

Jacob Harrison, Navid Asadizanjani, Mark M. Tehranipoor

Integr., 2021

FPGA-based Physical Unclonable Functions: A comprehensive overview of theory and architectures.

N. Nalla Anandakumar, Mohammad S. Hashmi, Mark M. Tehranipoor

Integr., 2021

An End-to-End Bitstream Tamper Attack Against Flip-Chip FPGAs.

Fahim Rahman, Farimah Farahmandi, Mark M. Tehranipoor

IACR Cryptol. ePrint Arch., 2021

What is All the FaaS About? - Remote Exploitation of FPGA-as-a-Service Platforms.

Nitin Pundir, Fahim Rahman, Farimah Farahmandi, Mark M. Tehranipoor

IACR Cryptol. ePrint Arch., 2021

SoC Security Properties and Rules.

Nusrat Farzana, Farimah Farahmandi, Mark M. Tehranipoor

IACR Cryptol. ePrint Arch., 2021

Quantifiable Assurance: From IPs to Platforms.

Bulbul Ahmed, Md Kawser Bepary, Nitin Pundir, Mike Borza, Oleg Raikhman, Amit Garg, Dale R. Donchin, Adam Cron, Mohamed A. Abdelmoneum, Farimah Farahmandi, Fahim Rahman, Mark M. Tehranipoor

IACR Cryptol. ePrint Arch., 2021

SAIF: Automated Asset Identification for Security Verification at the Register Transfer Level.

Nusrat Farzana, Avinash Ayalasomayajula, Fahim Rahman, Farimah Farahmandi, Mark M. Tehranipoor

Proceedings of the 39th IEEE VLSI Test Symposium, 2021

Special Session: CAD for Hardware Security - Automation is Key to Adoption of Solutions.

Sohrab Aftabjahani, Ryan Kastner, Mark M. Tehranipoor, Farimah Farahmandi, Jason Oberg, Anders Nordstrom, Nicole Fern, Alric Althoff

Proceedings of the 39th IEEE VLSI Test Symposium, 2021

SymbA: Symbolic Execution at C-level for Hardware Trojan Activation.

Arash Vafaei, Nick Hooten, Mark M. Tehranipoor, Farimah Farahmandi

Proceedings of the IEEE International Test Conference, 2021

LL-ATPG: Logic-Locking Aware Test Using Valet Keys in an Untrusted Environment.

M. Sazadur Rahman, Henian Li, Rui Guo, Fahim Rahman, Farimah Farahmandi, Mark M. Tehranipoor

Proceedings of the IEEE International Test Conference, 2021

HEXON: Protecting Firmware Using Hardware-Assisted Execution-Level Obfuscation.

Muhammad Monir Hossain, Sajeed Mohammad, Jason Vosatka, Jeffery S. Allen, Monica Allen, Farimah Farahmandi, Fahim Rahman, Mark M. Tehranipoor

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2021

Secure High-Level Synthesis: Challenges and Solutions.

Nitin Pundir, Farimah Farahmandi, Mark M. Tehranipoor

Proceedings of the 22nd International Symposium on Quality Electronic Design, 2021

AutoMap: Automated Mapping of Security Properties Between Different Levels of Abstraction in Design Flow.

Bulbul Ahmed, Fahim Rahman, Nick Hooten, Farimah Farahmandi, Mark M. Tehranipoor

Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2021

POCA: First Power-on Chip Authentication in Untrusted Foundry and Assembly.

Md Sami Ul Islam Sami, Fahim Rahman, Adam Cron, Dale R. Donchin, Mike Borza, Farimah Farahmandi, Mark M. Tehranipoor

Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust, 2021

RHAT: Efficient RowHammer-Aware Test for Modern DRAM Modules.

Mohammad Farmani, Mark M. Tehranipoor, Fahim Rahman

Proceedings of the 26th IEEE European Test Symposium, 2021

BOFT: Exploitable Buffer Overflow Detection by Information Flow Tracking.

Muhammad Monir Hossain, Farimah Farahmandi, Mark M. Tehranipoor, Fahim Rahman

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

PSC-TG: RTL Power Side-Channel Leakage Assessment with Test Pattern Generation.

Tao Zhang, Jungmin Park, Mark M. Tehranipoor, Farimah Farahmandi

Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021

Invited: End-to-End Secure SoC Lifecycle Management.

Md Sami Ul Islam Sami, Fahim Rahman, Farimah Farahmandi, Adam Cron, Mike Borza, Mark M. Tehranipoor

Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021

HLock: Locking IPs at the High-Level Language.

Md Rafid Muttaki, Roshanak Mohammadivojdan, Mark M. Tehranipoor, Farimah Farahmandi

Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021

2020

Interconnect-Based PUF With Signature Uniqueness Enhancement.

Liting Yu, Xiaoxiao Wang, Fahim Rahman, Mark M. Tehranipoor

IEEE Trans. Very Large Scale Integr. Syst., 2020

EMFORCED: EM-Based Fingerprinting Framework for Remarked and Cloned Counterfeit IC Detection Using Machine Learning Classification.

Andrew Stern, Ulbert Botero, Fahim Rahman, Domenic Forte, Mark M. Tehranipoor

IEEE Trans. Very Large Scale Integr. Syst., 2020

QEC: A Quantum Entropy Chip and Its Applications.

Jungmin Park, Seongjoon Cho, Taejin Lim, Mark M. Tehranipoor

IEEE Trans. Very Large Scale Integr. Syst., 2020

SCRIPT: A CAD Framework for Power Side-channel Vulnerability Assessment Using Information Flow Tracking and Pattern Generation.

Adib Nahiyan, Jungmin Park, Miao Tony He, Yousef Iskander, Farimah Farahmandi, Domenic Forte, Mark M. Tehranipoor

ACM Trans. Design Autom. Electr. Syst., 2020

Hidden in Plaintext: An Obfuscation-based Countermeasure against FPGA Bitstream Tampering Attacks.

Tamzidul Hoque, Kai Yang, Robert Karam, Shahin Tajik, Domenic Forte, Mark M. Tehranipoor, Swarup Bhunia

ACM Trans. Design Autom. Electr. Syst., 2020

Soft-HaT: Software-Based Silicon Reprogramming for Hardware Trojan Implementation.

Md. Mahbub Alam, Adib Nahiyan, Mehdi Sadi, Domenic Forte, Mark M. Tehranipoor

ACM Trans. Design Autom. Electr. Syst., 2020

CAS-Lock: A Security-Corruptibility Trade-off Resilient Logic Locking Scheme.

Bicky Shakya, Xiaolin Xu, Mark M. Tehranipoor, Domenic Forte

IACR Trans. Cryptogr. Hardw. Embed. Syst., 2020

A Physical Design Flow Against Front-Side Probing Attacks by Internal Shielding.

Huanyu Wang, Qihang Shi, Adib Nahiyan, Domenic Forte, Mark M. Tehranipoor

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

Special Issue: 2019 PAINE Conference - Physical Assurance and Inspection of Electronics.

Navid Asadi, Mark M. Tehranipoor

J. Hardw. Syst. Secur., 2020

Leveraging Side-Channel Information for Disassembly and Security.

Jungmin Park, Fahim Rahman, Apostol Vassilev, Domenic Forte, Mark M. Tehranipoor

ACM J. Emerg. Technol. Comput. Syst., 2020

The Big Hack Explained: Detection and Prevention of PCB Supply Chain Implants.

Dhwani Mehta, Hangwei Lu, Olivia P. Paradis, Mukhil Azhagan Mallaiyan Sathiaseelan, M. Tanjidur Rahman, Yousef Iskander, Praveen Chawla, Damon L. Woodard, Mark M. Tehranipoor, Navid Asadizanjani

ACM J. Emerg. Technol. Comput. Syst., 2020

Permutation Network De-obfuscation: A Delay-based Attack and Countermeasure Investigation.

Zimu Guo, Sreeja Chowdhury, Mark M. Tehranipoor, Domenic Forte

ACM J. Emerg. Technol. Comput. Syst., 2020

Defense-in-depth: A recipe for logic locking to prevail.

M. Tanjidur Rahman, M. Sazadur Rahman, Huanyu Wang, Shahin Tajik, Waleed Khalil, Farimah Farahmandi, Domenic Forte, Navid Asadizanjani, Mark M. Tehranipoor

Integr., 2020

Defeating CAS-Unlock.

Bicky Shakya, Xiaolin Xu, Mark M. Tehranipoor, Domenic Forte

IACR Cryptol. ePrint Arch., 2020

FICS-PCB: A Multi-Modal Image Dataset for Automated Printed Circuit Board Visual Inspection.

Hangwei Lu, Dhwani Mehta, Olivia P. Paradis, Navid Asadizanjani, Mark M. Tehranipoor, Damon L. Woodard

IACR Cryptol. ePrint Arch., 2020

RanStop: A Hardware-assisted Runtime Crypto-Ransomware Detection Technique.

Nitin Pundir, Mark M. Tehranipoor, Fahim Rahman

CoRR, 2020

Hardware Trust and Assurance through Reverse Engineering: A Survey and Outlook from Image Analysis and Machine Learning Perspectives.

Ulbert J. Botero, Ronald Wilson, Hangwei Lu, Mir Tanjidur Rahman, Mukhil Azhagan Mallaiyan Sathiaseelan, Fatemeh Ganji, Navid Asadizanjani, Mark M. Tehranipoor, Damon L. Woodard, Domenic Forte

CoRR, 2020

SeRFI: Secure Remote FPGA Initialization in an Untrusted Environment.

Adam Duncan, Adib Nahiyan, Fahim Rahman, Grant Skipper, Martin Swany, Andrew Lukefahr, Farimah Farahmandi, Mark M. Tehranipoor

Proceedings of the 38th IEEE VLSI Test Symposium, 2020

SPARTA: A Laser Probing Approach for Trojan Detection.

Andrew Stern, Dhwani Mehta, Shahin Tajik, Farimah Farahmandi, Mark M. Tehranipoor

Proceedings of the IEEE International Test Conference, 2020

On Optical Attacks Making Logic Obfuscation Fragile.

Leonidas Lavdas, M. Tanjidur Rahman, Mark M. Tehranipoor, Navid Asadizanjani

Proceedings of the IEEE International Test Conference in Asia, 2020

The Key is Left under the Mat: On the Inappropriate Security Assumption of Logic Locking Schemes.

M. Tanjidur Rahman, Shahin Tajik, M. Sazadur Rahman, Mark M. Tehranipoor, Navid Asadizanjani

Proceedings of the 2020 IEEE International Symposium on Hardware Oriented Security and Trust, 2020

The Pursuit of Happiness: Establishing Hardware Root-of-Trust for Cyber Security.

Mark M. Tehranipoor

Proceedings of the 4th ACM Workshop on Attacks and Solutions in Hardware Security Workshop, 2020

2019

Probing Assessment Framework and Evaluation of Antiprobing Solutions.

Huanyu Wang, Qihang Shi, Domenic Forte, Mark M. Tehranipoor

IEEE Trans. Very Large Scale Integr. Syst., 2019

System-Level Counterfeit Detection Using On-Chip Ring Oscillator Array.

Xiaoxiao Wang, Yueying Han, Mark M. Tehranipoor

IEEE Trans. Very Large Scale Integr. Syst., 2019

Editorial TVLSI Positioning - Continuing and Accelerating an Upward Trajectory.

Massimo Alioto, Magdy S. Abadir, Tughrul Arslan, Chirn Chye Boon, Andreas Burg, Chip-Hong Chang, Meng-Fan Chang, Yao-Wen Chang, Poki Chen, Pasquale Corsonello, Paolo Crovetti, Shiro Dosho, Rolf Drechsler, Ibrahim Abe M. Elfadel, Ruonan Han, Masanori Hashimoto, Chun-Huat Heng, Deukhyoun Heo, Tsung-Yi Ho, Houman Homayoun, Yuh-Shyan Hwang, Ajay Joshi, Rajiv V. Joshi, Tanay Karnik, Chulwoo Kim, Tony Tae-Hyoung Kim, Jaydeep Kulkarni, Volkan Kursun, Yoonmyung Lee, Hai Helen Li, Huawei Li, Prabhat Mishra, Baker Mohammad, Mehran Mozaffari Kermani, Makoto Nagata, Koji Nii, Partha Pratim Pande, Bipul C. Paul, Vasilis F. Pavlidis, José Pineda de Gyvez, Ioannis Savidis, Patrick Schaumont, Fabio Sebastiano, Anirban Sengupta, Mingoo Seok, Mircea R. Stan, Mark M. Tehranipoor, Aida Todri-Sanial, Marian Verhelst, Valerio Vignoli, Xiaoqing Wen, Jiang Xu, Wei Zhang, Zhengya Zhang, Jun Zhou, Mark Zwolinski, Stacey Weber

IEEE Trans. Very Large Scale Integr. Syst., 2019

Recycled FPGA Detection Using Exhaustive LUT Path Delay Characterization and Voltage Scaling.

Md. Mahbub Alam, Mark M. Tehranipoor, Domenic Forte

IEEE Trans. Very Large Scale Integr. Syst., 2019

Electronics Supply Chain Integrity Enabled by Blockchain.

Xiaolin Xu, Fahim Rahman, Bicky Shakya, Apostol Vassilev, Domenic Forte, Mark M. Tehranipoor

ACM Trans. Design Autom. Electr. Syst., 2019

Emerging Attacks and Solutions for Secure Hardware in the Internet of Things.

Chip-Hong Chang, Marten van Dijk, Ulrich Rührmair, Mark M. Tehranipoor

IEEE Trans. Dependable Secur. Comput., 2019

Covert Gates: Protecting Integrated Circuits with Undetectable Camouflaging.

Bicky Shakya, Hao-Ting Shen, Mark M. Tehranipoor, Domenic Forte

IACR Trans. Cryptogr. Hardw. Embed. Syst., 2019

Obfuscated Built-In Self-Authentication With Secure and Efficient Wire-Lifting.

Qihang Shi, Mark M. Tehranipoor, Domenic Forte

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019

Security-Aware FSM Design Flow for Identifying and Mitigating Vulnerabilities to Fault Attacks.

Adib Nahiyan, Farimah Farahmandi, Prabhat Mishra, Domenic Forte, Mark M. Tehranipoor

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019

Standards for Hardware Security.

Ujjwal Guin, Navid Asadizanjani, Mark M. Tehranipoor

GetMobile Mob. Comput. Commun., 2019

Dynamically Obfuscated Scan Chain To Resist Oracle-Guided Attacks On Logic Locked Design.

M. Sazadur Rahman, Adib Nahiyan, Sarah Amir, Fahim Rahman, Farimah Farahmandi, Domenic Forte, Mark M. Tehranipoor

IACR Cryptol. ePrint Arch., 2019

Theoretical and Practical Approaches for Hardness Amplification of PUFs.

Fatemeh Ganji, Shahin Tajik, Pascal Stauss, Jean-Pierre Seifert, Domenic Forte, Mark M. Tehranipoor

IACR Cryptol. ePrint Arch., 2019

Upgrade/Downgrade: Efficient and Secure Legacy Electronic System Replacement.

Ulbert J. Botero, Mark M. Tehranipoor, Domenic Forte

IEEE Des. Test, 2019

EOP: An Encryption-Obfuscation Solution for Protecting PCBs Against Tampering and Reverse Engineering.

Zimu Guo, Xiaolin Xu, Mark M. Tehranipoor, Domenic Forte

CoRR, 2019

Unlock Your Heart: Next Generation Biometric in Resource-Constrained Healthcare Systems and IoT.

Nima Karimian, Mark M. Tehranipoor, Damon L. Woodard, Domenic Forte

IEEE Access, 2019

RTL-PSC: Automated Power Side-Channel Leakage Assessment at Register-Transfer Level.

Miao Tony He, Jungmin Park, Adib Nahiyan, Apostol Vassilev, Yier Jin, Mark M. Tehranipoor

Proceedings of the 37th IEEE VLSI Test Symposium, 2019

Rock'n'roll PUFs: Crafting Provably Secure PUFs from Less Secure Ones.

Fatemeh Ganji, Shahin Tajik, Pascal Stauss, Jean-Pierre Seifert, Domenic Forte, Mark M. Tehranipoor

Proceedings of 8th International Workshop on Security Proofs for Embedded Systems, 2019

IEEE International Symposium on Hardware Oriented Security and Trust (HOST): Past, Present, and Future.

Domenic Forte, Swarup Bhunia, Ramesh Karri, Jim Plusquellic, Mark M. Tehranipoor

Proceedings of the IEEE International Test Conference, 2019

SoC Security Verification using Property Checking.

Nusrat Farzana, Fahim Rahman, Mark M. Tehranipoor, Farimah Farahmandi

Proceedings of the IEEE International Test Conference, 2019

FPGA Bitstream Security: A Day in the Life.

Adam Duncan, Fahim Rahman, Andrew Lukefahr, Farimah Farahmandi, Mark M. Tehranipoor

Proceedings of the IEEE International Test Conference, 2019

SCR-QRNG: Side-Channel Resistant Design using Quantum Random Number Generator.

Jungmin Park, Seongjoon Cho, Taejin Lim, Swarup Bhunia, Mark M. Tehranipoor

Proceedings of the International Conference on Computer-Aided Design, 2019

QIF-Verilog: Quantitative Information-Flow based Hardware Description Languages for Pre-Silicon Security Assessment.

Xiaolong Guo, Raj Gautam Dutta, Jiaji He, Mark M. Tehranipoor, Yier Jin

Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust, 2019

FLATS: Filling Logic and Testing Spatially for FPGA Authentication and Tamper Detection.

Adam Duncan, Grant Skipper, Andrew Stern, Adib Nahiyan, Fahim Rahman, Andrew Lukefahr, Mark M. Tehranipoor, Martin Swany

Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust, 2019

LPN-based Device Authentication Using Resistive Memory.

Md Tanvir Arafin, Hao-Ting Shen, Mark M. Tehranipoor, Gang Qu

Proceedings of the 2019 on Great Lakes Symposium on VLSI, 2019

RAM-Jam: Remote Temperature and Voltage Fault Attack on FPGAs using Memory Collisions.

Md. Mahbub Alam, Shahin Tajik, Fatemeh Ganji, Mark M. Tehranipoor, Domenic Forte

Proceedings of the 2019 Workshop on Fault Diagnosis and Tolerance in Cryptography, 2019

A Metal-Via Resistance Based Physically Unclonable Function with 1.18% Native Instability.

Beomsoo Park, Mark M. Tehranipoor, Domenic Forte, Nima Maghari

Proceedings of the IEEE Custom Integrated Circuits Conference, 2019

2018

An On-Chip Dynamically Obfuscated Wrapper for Protecting Supply Chain Against IP and IC Piracies.

Dongrong Zhang, Xiaoxiao Wang, Md. Tauhidur Rahman, Mark M. Tehranipoor

IEEE Trans. Very Large Scale Integr. Syst., 2018

Bimodal Oscillation as a Mechanism for Autonomous Majority Voting in PUFs.

Xiaolin Xu, Shahrzad Keshavarz, Domenic Forte, Mark M. Tehranipoor, Daniel E. Holcomb

IEEE Trans. Very Large Scale Integr. Syst., 2018

SCARe: An SRAM-Based Countermeasure Against IC Recycling.

Zimu Guo, Xiaolin Xu, Md. Tauhidur Rahman, Mark M. Tehranipoor, Domenic Forte

IEEE Trans. Very Large Scale Integr. Syst., 2018

Hardware-Enabled Pharmaceutical Supply Chain Security.

Kun Yang, Hao-Ting Shen, Domenic Forte, Swarup Bhunia, Mark M. Tehranipoor

ACM Trans. Design Autom. Electr. Syst., 2018

ReSC: An RFID-Enabled Solution for Defending IoT Supply Chain.

Kun Yang, Domenic Forte, Mark M. Tehranipoor

ACM Trans. Design Autom. Electr. Syst., 2018

UCR: An Unclonable Environmentally Sensitive Chipless RFID Tag For Protecting Supply Chain.

Kun Yang, Ulbert Botero, Hao-Ting Shen, Damon L. Woodard, Domenic Forte, Mark M. Tehranipoor

ACM Trans. Design Autom. Electr. Syst., 2018

Secure Scan and Test Using Obfuscation Throughout Supply Chain.

Xiaoxiao Wang, Dongrong Zhang, Miao Tony He, Donglin Su, Mark M. Tehranipoor

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

System-on-Chip Platform Security Assurance: Architecture and Validation.

Sandip Ray, Eric Peeters, Mark M. Tehranipoor, Swarup Bhunia

Proc. IEEE, 2018

Detecting Hardware Trojans Inserted by Untrusted Foundry Using Physical Inspection and Advanced Image Processing.

Nidish Vashistha, M. Tanjidur Rahman, Hao-Ting Shen, Damon L. Woodard, Navid Asadizanjani, Mark M. Tehranipoor

J. Hardw. Syst. Secur., 2018

Development and Evaluation of Hardware Obfuscation Benchmarks.

Sarah Amir, Bicky Shakya, Xiaolin Xu, Yier Jin, Swarup Bhunia, Mark M. Tehranipoor, Domenic Forte

J. Hardw. Syst. Secur., 2018

Challenges and Opportunities in Analog and Mixed Signal (AMS) Integrated Circuit (IC) Security.

Md. Mahbub Alam, Sreeja Chowdhury, Beomsoo Park, David Joseph Munzer, Nima Maghari, Mark M. Tehranipoor, Domenic Forte

J. Hardw. Syst. Secur., 2018

LDPUF: Exploiting DRAM Latency Variations to Generate Robust Device Signatures.

Bashir M. Sabquat Bahar Talukder, Biswajit Ray, Mark M. Tehranipoor, Domenic Forte, Md. Tauhidur Rahman

CoRR, 2018

Secure and Reliable Biometric Access Control for Resource-Constrained Systems and IoT.

Nima Karimian, Zimu Guo, Fatemeh Tehranipoor, Damon L. Woodard, Mark M. Tehranipoor, Domenic Forte

CoRR, 2018

Physical Inspection & Attacks: New Frontier in Hardware Security.

M. Tanjidur Rahman, Qihang Shi, Shahin Tajik, Hao-Ting Shen, Damon L. Woodard, Mark M. Tehranipoor, Navid Asadizanjani

Proceedings of the 3rd IEEE International Verification and Security Workshop, 2018

EMFORCED: EM-based Fingerprinting Framework for Counterfeit Detection with Demonstration on Remarked and Cloned ICs.

Andrew Stern, Ulbert Botero, Bicky Shakya, Hao-Ting Shen, Domenic Forte, Mark M. Tehranipoor

Proceedings of the IEEE International Test Conference, 2018

Robust Timing Attack Countermeasure on Virtual Hardware.

Kai Yang, Jungmin Park, Mark M. Tehranipoor, Swarup Bhunia

Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI, 2018

Hardware virtualization for protection against power analysis attack.

Kai Yang, Jungmin Park, Mark M. Tehranipoor, Swarup Bhunia

Proceedings of the 2018 IEEE International Symposium on Hardware Oriented Security and Trust, 2018

Robust, low-cost, and accurate detection of recycled ICs using digital signatures.

Mahabubul Alam, Sreeja Chowdhury, Mark M. Tehranipoor, Ujjwal Guin

Proceedings of the 2018 IEEE International Symposium on Hardware Oriented Security and Trust, 2018

Device attestation: Past, present, and future.

Orlando Arias, Fahim Rahman, Mark M. Tehranipoor, Yier Jin

Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

Power-based side-channel instruction-level disassembler.

Jungmin Park, Xiaolin Xu, Yier Jin, Domenic Forte, Mark M. Tehranipoor

Proceedings of the 55th Annual Design Automation Conference, 2018

CIPA: Concurrent IC and PCB Authentication Using On-chip Ring Oscillator Array.

Yueying Han, Xiaoxiao Wang, Mark M. Tehranipoor

Proceedings of the 27th IEEE Asian Test Symposium, 2018

A Comprehensive Analysis on Vulnerability of Active Shields to Tilted Microprobing Attacks.

Qihang Shi, Huanyu Wang, Navid Asadizanjani, Mark M. Tehranipoor, Domenic Forte

Proceedings of the Asian Hardware Oriented Security and Trust Symposium, 2018

2017

Poly-Si-Based Physical Unclonable Functions.

Hao-Ting Shen, Fahim Rahman, Bicky Shakya, Xiaolin Xu, Mark M. Tehranipoor, Domenic Forte

IEEE Trans. Very Large Scale Integr. Syst., 2017

Design of Reliable SoCs With BIST Hardware and Machine Learning.

Mehdi Sadi, Gustavo K. Contreras, Jifeng Chen, LeRoy Winemberg, Mark M. Tehranipoor

IEEE Trans. Very Large Scale Integr. Syst., 2017

Security Beyond CMOS: Fundamentals, Applications, and Roadmap.

Fahim Rahman, Bicky Shakya, Xiaolin Xu, Domenic Forte, Mark M. Tehranipoor

IEEE Trans. Very Large Scale Integr. Syst., 2017

Test-Point Insertion Efficiency Analysis for LBIST in High-Assurance Applications.

Miao Tony He, Gustavo K. Contreras, Dat Tran, LeRoy Winemberg, Mark M. Tehranipoor

IEEE Trans. Very Large Scale Integr. Syst., 2017

Editorial.

Krishnendu Chakrabarty, Massimo Alioto, Bevan M. Baas, Chirn Chye Boon, Meng-Fan Chang, Naehyuck Chang, Yao-Wen Chang, Chip-Hong Chang, Shih-Chieh Chang, Poki Chen, Masud H. Chowdhury, Pasquale Corsonello, Ibrahim Abe M. Elfadel, Said Hamdioui, Masanori Hashimoto, Tsung-Yi Ho, Houman Homayoun, Yuh-Shyan Hwang, Rajiv V. Joshi, Tanay Karnik, Mehran Mozaffari Kermani, Chulwoo Kim, Tae-Hyoung Kim, Jaydeep P. Kulkarni, Eren Kursun, Erik Larsson, Hai (Helen) Li, Huawei Li, Patrick P. Mercier, Prabhat Mishra, Makoto Nagata, Arun S. Natarajan, Koji Nii, Partha Pratim Pande, Ioannis Savidis, Mingoo Seok, Sheldon X.-D. Tan, Mark M. Tehranipoor, Aida Todri-Sanial, Miroslav N. Velev, Xiaoqing Wen, Jiang Xu, Wei Zhang, Zhengya Zhang, Stacey Weber Jackson

IEEE Trans. Very Large Scale Integr. Syst., 2017

CDTA: A Comprehensive Solution for Counterfeit Detection, Traceability, and Authentication in the IoT Supply Chain.

Kun Yang, Domenic Forte, Mark M. Tehranipoor

ACM Trans. Design Autom. Electr. Syst., 2017

Obfuscation-Based Protection Framework against Printed Circuit Boards Unauthorized Operation and Reverse Engineering.

Zimu Guo, Jia Di, Mark M. Tehranipoor, Domenic Forte

ACM Trans. Design Autom. Electr. Syst., 2017

Introduction to Cyber-Physical System Security: A Cross-Layer Perspective.

Jacob Wurm, Yier Jin, Yang Liu, Shiyan Hu, Kenneth Heffner, Fahim Rahman, Mark M. Tehranipoor

IEEE Trans. Multi Scale Comput. Syst., 2017

SMA: A System-Level Mutual Authentication for Protecting Electronic Hardware and Firmware.

Ujjwal Guin, Swarup Bhunia, Domenic Forte, Mark M. Tehranipoor

IEEE Trans. Dependable Secur. Comput., 2017

TRO: An On-Chip Ring Oscillator-Based GHz Transient IR-Drop Monitor.

Xiaoxiao Wang, Pengyuan Jiao, Mehdi Sadi, Donglin Su, LeRoy Winemberg, Mark M. Tehranipoor

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017

SoC Speed Binning Using Machine Learning and On-Chip Slack Sensors.

Mehdi Sadi, Sukeshwar Kannan, LeRoy Winemberg, Mark M. Tehranipoor

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017

Highly Reliable Key Generation From Electrocardiogram (ECG).

Nima Karimian, Zimu Guo, Mark M. Tehranipoor, Domenic Forte

IEEE Trans. Biomed. Eng., 2017

Benchmarking of Hardware Trojans and Maliciously Affected Circuits.

Bicky Shakya, Miao Tony He, Hassan Salmani, Domenic Forte, Swarup Bhunia, Mark M. Tehranipoor

J. Hardw. Syst. Secur., 2017

Systematic Correlation and Cell Neighborhood Analysis of SRAM PUF for Robust and Unique Key Generation.

Md. Tauhidur Rahman, Alison Hosey, Zimu Guo, Jackson Carroll, Domenic Forte, Mark M. Tehranipoor

J. Hardw. Syst. Secur., 2017

Editorial for the Introductory Issue of the <i>Journal of Hardware and Systems Security</i> (HaSS).

Swarup Bhunia, Mark M. Tehranipoor

J. Hardw. Syst. Secur., 2017

TSensors Vision, Infrastructure and Security Challenges in Trillion Sensor Era.

Mahabubul Alam, Mark M. Tehranipoor, Ujjwal Guin

J. Hardw. Syst. Secur., 2017

Novel Bypass Attack and BDD-based Tradeoff Analysis Against all Known Logic Locking Attacks.

Xiaolin Xu, Bicky Shakya, Mark M. Tehranipoor, Domenic Forte

IACR Cryptol. ePrint Arch., 2017

An Access Mechanism for Embedded Sensors in Modern SoCs.

Miao Tony He, Mark M. Tehranipoor

J. Electron. Test., 2017

Probing Attacks on Integrated Circuits: Challenges and Research Opportunities.

Huanyu Wang, Domenic Forte, Mark M. Tehranipoor, Qihang Shi

IEEE Des. Test, 2017

Dynamically obfuscated scan for protecting IPs against scan-based attacks throughout supply chain.

Dongrong Zhang, Miao Tony He, Xiaoxiao Wang, Mark M. Tehranipoor

Proceedings of the 35th IEEE VLSI Test Symposium, 2017

Aging resilient RO PUF with increased reliability in FPGA.

Sreeja Chowdhury, Xiaolin Xu, Mark M. Tehranipoor, Domenic Forte

Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2017

ATAVE: A framework for automatic timing attack vulnerability evaluation.

Jungmin Park, Massimiliano Corba, Antonio E. de la Sema, Richard L. Vigeant, Mark M. Tehranipoor, Swarup Bhunia

Proceedings of the IEEE 60th International Midwest Symposium on Circuits and Systems, 2017

iPUF: Interconnect PUF with Self-Masking Circuit for Performance Enhancement.

Liting Yu, Xiaoxiao Wang, Fahim Rahman, Mark M. Tehranipoor

Proceedings of the 18th International Workshop on Microprocessor and SOC Test and Verification, 2017

Hardware-Assisted Cybersecurity for IoT Devices.

Fahim Rahman, Mohammad Farmani, Mark M. Tehranipoor, Yier Jin

Proceedings of the 18th International Workshop on Microprocessor and SOC Test and Verification, 2017

Hardware trojan detection through information flow security verification.

Adib Nahiyan, Mehdi Sadi, Rahul Vittal, Gustavo K. Contreras, Domenic Forte, Mark M. Tehranipoor

Proceedings of the IEEE International Test Conference, 2017

Design of a digital IP for 3D-IC die-to-die clock synchronization.

Mehdi Sadi, Sukeshwar Kannan, Luke England, Mark M. Tehranipoor

Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

Human recognition from photoplethysmography (PPG) based on non-fiducial features.

Nima Karimian, Zimu Guo, Mark M. Tehranipoor, Domenic Forte

Proceedings of the 2017 IEEE International Conference on Acoustics, 2017

A stochastic all-digital weak physically unclonable function for analog/mixed-signal applications.

Troy Bryant, Sreeja Chowdhury, Domenic Forte, Mark M. Tehranipoor, Nima Maghari

Proceedings of the 2017 IEEE International Symposium on Hardware Oriented Security and Trust, 2017

Securing Split Manufactured ICs with Wire Lifting Obfuscated Built-In Self-Authentication.

Qihang Shi, Kan Xiao, Domenic Forte, Mark M. Tehranipoor

Proceedings of the on Great Lakes Symposium on VLSI 2017, 2017

Comparative Analysis of Hardware Obfuscation for IP Protection.

Sarah Amir, Bicky Shakya, Domenic Forte, Mark M. Tehranipoor, Swarup Bhunia

Proceedings of the on Great Lakes Symposium on VLSI 2017, 2017

FFD: A Framework for Fake Flash Detection.

Zimu Guo, Xiaolin Xu, Mark M. Tehranipoor, Domenic Forte

Proceedings of the 54th Annual Design Automation Conference, 2017

Standardizing Bad Cryptographic Practice: A Teardown of the IEEE Standard for Protecting Electronic-design Intellectual Property.

Animesh Chhotaray, Adib Nahiyan, Thomas Shrimpton, Domenic Forte, Mark M. Tehranipoor

Proceedings of the 2017 ACM SIGSAC Conference on Computer and Communications Security, 2017

ASHES 2017: Workshop on Attacks and Solutions in Hardware Security.

Chip-Hong Chang, Marten van Dijk, Farinaz Koushanfar, Ulrich Rührmair, Mark M. Tehranipoor

Proceedings of the 2017 ACM SIGSAC Conference on Computer and Communications Security, 2017

Non-fiducial PPG-based authentication for healthcare application.

Nima Karimian, Mark M. Tehranipoor, Domenic Forte

Proceedings of the 2017 IEEE EMBS International Conference on Biomedical & Health Informatics, 2017

MUTARCH: Architectural diversity for FPGA device and IP security.

Robert Karam, Tamzidul Hoque, Sandip Ray, Mark M. Tehranipoor, Swarup Bhunia

Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017

Security vulnerability analysis of design-for-test exploits for asset protection in SoCs.

Gustavo K. Contreras, Adib Nahiyan, Swarup Bhunia, Domenic Forte, Mark M. Tehranipoor

Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017

A split manufacturing approach for unclonable chipless RFIDs for pharmaceutical supply chain security.

Kun Yang, Ulbert Botero, Hao-Ting Shen, Domenic Forte, Mark M. Tehranipoor

Proceedings of the 2017 Asian Hardware Oriented Security and Trust Symposium, 2017

DOST: Dynamically obfuscated wrapper for split test against IC piracy.

Xiaoxiao Wang, Yueyu Guo, Tauhid Ramhan, Dongrong Zhang, Mark M. Tehranipoor

Proceedings of the 2017 Asian Hardware Oriented Security and Trust Symposium, 2017

MPA: Model-assisted PCB attestation via board-level RO and temperature compensation.

Zimu Guo, Xiaolin Xu, Mark M. Tehranipoor, Domenic Forte

Proceedings of the 2017 Asian Hardware Oriented Security and Trust Symposium, 2017

2016

A Novel Peak Power Supply Noise Measurement and Adaptation System for Integrated Circuits.

Xiaoxiao Wang, Dongrong Zhang, Donglin Su, LeRoy Winemberg, Mark M. Tehranipoor

IEEE Trans. Very Large Scale Integr. Syst., 2016

Design of a Network of Digital Sensor Macros for Extracting Power Supply Noise Profile in SoCs.

Mehdi Sadi, Mark M. Tehranipoor

IEEE Trans. Very Large Scale Integr. Syst., 2016

Design of Accurate Low-Cost On-Chip Structures for Protecting Integrated Circuits Against Recycling.

Ujjwal Guin, Domenic Forte, Mark M. Tehranipoor

IEEE Trans. Very Large Scale Integr. Syst., 2016

Hardware Trojans: Lessons Learned after One Decade of Research.

Kan Xiao, Domenic Forte, Yier Jin, Ramesh Karri, Swarup Bhunia, Mark M. Tehranipoor

ACM Trans. Design Autom. Electr. Syst., 2016

FORTIS: A Comprehensive Solution for Establishing Forward Trust for Protecting IPs and ICs.

Ujjwal Guin, Qihang Shi, Domenic Forte, Mark M. Tehranipoor

ACM Trans. Design Autom. Electr. Syst., 2016

Security and Vulnerability Implications of 3D ICs.

Yang Xie, Chongxi Bao, Caleb Serafy, Tiantao Lu, Ankur Srivastava, Mark M. Tehranipoor

IEEE Trans. Multi Scale Comput. Syst., 2016

Guest Editorial: Hardware/Software Cross-Layer Technologies for Trustworthy and Secure Computing.

Shiyan Hu, Yier Jin, Kenneth Heffner, Mark M. Tehranipoor

IEEE Trans. Multi Scale Comput. Syst., 2016

Vulnerability Analysis of a Circuit Layout to Hardware Trojan Insertion.

Hassan Salmani, Mark M. Tehranipoor

IEEE Trans. Inf. Forensics Secur., 2016

An Aging-Resistant RO-PUF for Reliable Key Generation.

Md. Tauhidur Rahman, Fahim Rahman, Domenic Forte, Mark M. Tehranipoor

IEEE Trans. Emerg. Top. Comput., 2016

A Survey on Chip to System Reverse Engineering.

Shahed E. Quadir, Junlin Chen, Domenic Forte, Navid Asadizanjani, Sina Shahbazmohamadi, Lei Wang, John A. Chandy, Mark M. Tehranipoor

ACM J. Emerg. Technol. Comput. Syst., 2016

Hardware Security (Dagstuhl Seminar 16202).

Osnat Keren, Ilia Polian, Mark M. Tehranipoor

Dagstuhl Reports, 2016

Security Rule Checking in IC Design.

Kan Xiao, Adib Nahiyan, Mark M. Tehranipoor

Computer, 2016

Security validation in IoT space.

Sandip Ray, Swarup Bhunia, Yier Jin, Mark M. Tehranipoor

Proceedings of the 34th IEEE VLSI Test Symposium, 2016

Test-point insertion efficiency analysis for LBIST applications.

Miao Tony He, Gustavo K. Contreras, Mark M. Tehranipoor, Dat Tran, LeRoy Winemberg

Proceedings of the 34th IEEE VLSI Test Symposium, 2016

New Directions in Hardware Security.

Mark M. Tehranipoor

Proceedings of the 29th International Conference on VLSI Design and 15th International Conference on Embedded Systems, 2016

Robust bitstream protection in FPGA-based systems through low-overhead obfuscation.

Robert Karam, Tamzidul Hoque, Sandip Ray, Mark M. Tehranipoor, Swarup Bhunia

Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2016

Technical demonstration session: Software toolflow for FPGA bitstream obfuscation.

Robert Karam, Tamzidul Hoque, Sandip Ray, Mark M. Tehranipoor, Swarup Bhunia

Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2016

A stochastic approach to analog physical unclonable function.

Troy Bryant, Sreeja Chowdhury, Domenic Forte, Mark M. Tehranipoor, Nima Maghari

Proceedings of the IEEE 59th International Midwest Symposium on Circuits and Systems, 2016

BIST-RM: BIST-assisted reliability management of SoCs using on-chip clock sweeping and machine learning.

Mehdi Sadi, Gustavo K. Contreras, Dat Tran, Jifeng Chen, LeRoy Winemberg, Mark M. Tehranipoor

Proceedings of the 2016 IEEE International Test Conference, 2016

Recycled FPGA detection using exhaustive LUT path delay characterization.

Md. Mahbub Alam, Mark M. Tehranipoor, Domenic Forte

Proceedings of the 2016 IEEE International Test Conference, 2016

Selective Enhancement of Randomness at the Materials Level: Poly-Si Based Physical Unclonable Functions (PUFs).

Hao-Ting Shen, Fahim Rahman, Bicky Shakya, Mark M. Tehranipoor, Domenic Forte

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016

An efficient all-digital IR-Drop Alarmer for DVFS-based SoC.

Liting Yu, Xiaoxiao Wang, Yuanqing Cheng, Xiaoying Zhao, Pengyuan Jiao, Aixin Chen, Donglin Su, LeRoy Winemberg, Mehdi Sadi, Mark M. Tehranipoor

Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

AES design improvement towards information safety.

Liang Wu, Xiaoxiao Wang, Xiaoying Zhao, Yuanqing Cheng, Donglin Su, Aixin Chen, Qihang Shi, Mark M. Tehranipoor

Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

Gate-level netlist reverse engineering for hardware security: Control logic register identification.

Travis Meade, Yier Jin, Mark M. Tehranipoor, Shaojie Zhang

Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

Hardware security meets biometrics for the age of IoT.

Zimu Guo, Nima Karimian, Mark M. Tehranipoor, Domenic Forte

Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

Chip editor: leveraging circuit edit for logic obfuscation and trusted fabrication.

Bicky Shakya, Navid Asadizanjani, Domenic Forte, Mark M. Tehranipoor

Proceedings of the 35th International Conference on Computer-Aided Design, 2016

UCR: An unclonable chipless RFID tag.

Kun Yang, Domenic Forte, Mark M. Tehranipoor

Proceedings of the 2016 IEEE International Symposium on Hardware Oriented Security and Trust, 2016

A layout-driven framework to assess vulnerability of ICs to microprobing attacks.

Qihang Shi, Navid Asadizanjani, Domenic Forte, Mark M. Tehranipoor

Proceedings of the 2016 IEEE International Symposium on Hardware Oriented Security and Trust, 2016

Enhancing noise sensitivity of embedded SRAMs for robust true random number generation in SoCs.

Md. Tauhidur Rahman, Domenic Forte, Xiaoxiao Wang, Mark M. Tehranipoor

Proceedings of the 2016 IEEE Asian Hardware-Oriented Security and Trust, 2016

Aging attacks for key extraction on permutation-based obfuscation.

Zimu Guo, Mark M. Tehranipoor, Domenic Forte

Proceedings of the 2016 IEEE Asian Hardware-Oriented Security and Trust, 2016

A zero-cost approach to detect recycled SoC chips using embedded SRAM.

Zimu Guo, Md. Tauhidur Rahman, Mark M. Tehranipoor, Domenic Forte

Proceedings of the 2016 IEEE International Symposium on Hardware Oriented Security and Trust, 2016

Tracking Data Flow at Gate-Level through Structural Checking.

Thao Le, Jia Di, Mark M. Tehranipoor, Domenic Forte, Lei Wang

Proceedings of the 26th edition on Great Lakes Symposium on VLSI, 2016

AVFSM: a framework for identifying and mitigating vulnerabilities in FSMs.

Adib Nahiyan, Kan Xiao, Kun Yang, Yier Jin, Domenic Forte, Mark M. Tehranipoor

Proceedings of the 53rd Annual Design Automation Conference, 2016

2015

Aging Adaption in Integrated Circuits Using a Novel Built-In Sensor.

Xiaoxiao Wang, LeRoy Winemberg, Donglin Su, Dat Tran, Saji George, Nisar Ahmed, Steve Palosh, Allan Dobin, Mark M. Tehranipoor

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015

Detecting Hardware Trojans using On-chip Sensors in an ASIC Design.

Shane Kelly, Xuehui Zhang, Mohammad Tehranipoor, Andrew Ferraiuolo

J. Electron. Test., 2015

A robust digital sensor IP and sensor insertion flow for in-situ path timing slack monitoring in SoCs.

Mehdi Sadi, LeRoy Winemberg, Mark M. Tehranipoor

Proceedings of the 33rd IEEE VLSI Test Symposium, 2015

ReSC: RFID-Enabled Supply Chain Management and Traceability for Network Devices.

Kun Yang, Domenic Forte, Mark M. Tehranipoor

Proceedings of the Radio Frequency Identification. Security and Privacy Issues, 2015

Harnessing Nanoscale Device Properties for Hardware Security.

Bicky Shakya, Fahim Rahman, Mark M. Tehranipoor, Domenic Forte

Proceedings of the 16th International Workshop on Microprocessor and SOC Test and Verification, 2015

LBIST pattern reduction by learning ATPG test cube properties.

Gustavo K. Contreras, Yang Zhao, Nisar Ahmed, LeRoy Winemberg, Mohammad Tehranipoor

Proceedings of the Sixteenth International Symposium on Quality Electronic Design, 2015

Performance optimization for on-chip sensors to detect recycled ICs.

Bicky Shakya, Ujjwal Guin, Mark M. Tehranipoor, Domenic Forte

Proceedings of the 33rd IEEE International Conference on Computer Design, 2015

A pair selection algorithm for robust RO-PUF against environmental variations and aging.

Md. Tauhidur Rahman, Domenic Forte, Fahim Rahman, Mark M. Tehranipoor

Proceedings of the 33rd IEEE International Conference on Computer Design, 2015

Protecting Endpoint Devices in IoT Supply Chain.

Kun Yang, Domenic Forte, Mark M. Tehranipoor

Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2015

Efficient and secure split manufacturing via obfuscated built-in self-authentication.

Kan Xiao, Domenic Forte, Mark M. Tehranipoor

Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust, 2015

Speed Binning Using Machine Learning And On-chip Slack Sensors.

Mehdi Sadi, Mark M. Tehranipoor, Xiaoxiao Wang, LeRoy Winemberg

Proceedings of the 25th edition on Great Lakes Symposium on VLSI, GLVLSI 2015, Pittsburgh, PA, USA, May 20, 2015

Predictive LBIST model and partial ATPG for seed extraction.

Gustavo K. Contreras, Nisar Ahmed, LeRoy Winemberg, Mark M. Tehranipoor

Proceedings of the 2015 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2015

Chip-level anti-reverse engineering using transformable interconnects.

Shuai Chen, Junlin Chen, Domenic Forte, Jia Di, Mark M. Tehranipoor, Lei Wang

Proceedings of the 2015 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2015

Investigation of obfuscation-based anti-reverse engineering for printed circuit boards.

Zimu Guo, Mark M. Tehranipoor, Domenic Forte, Jia Di

Proceedings of the 52nd Annual Design Automation Conference, 2015

2014

Design of On-Chip Lightweight Sensors for Effective Detection of Recycled ICs.

Xuehui Zhang, Mohammad Tehranipoor

IEEE Trans. Very Large Scale Integr. Syst., 2014

Light-Weight On-Chip Structure for Measuring Timing Uncertainty Induced by Noise in Integrated Circuits.

Shuo Wang, Mohammad Tehranipoor

IEEE Trans. Very Large Scale Integr. Syst., 2014

A Novel Built-In Self-Authentication Technique to Prevent Inserting Hardware Trojans.

Kan Xiao, Domenic Forte, Mohammad Tehranipoor

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014

Counterfeit Integrated Circuits: A Rising Threat in the Global Semiconductor Supply Chain.

Ujjwal Guin, Ke Huang, Daniel DiMase, John M. Carulli, Mohammad Tehranipoor, Yiorgos Makris

Proc. IEEE, 2014

Critical-reliability path identification and delay analysis.

Jifeng Chen, Shuo Wang, Mohammad Tehranipoor

ACM J. Emerg. Technol. Comput. Syst., 2014

Guest Editorial.

Ilia Polian, Mohammad Tehranipoor

IET Comput. Digit. Tech., 2014

On Achieving Capture Power Safety in At-Speed Scan-Based Logic BIST.

Akihiro Tomita, Xiaoqing Wen, Yasuo Sato, Seiji Kajihara, Kohei Miyase, Stefan Holst, Patrick Girard, Mohammad Tehranipoor, Laung-Terng Wang

IEICE Trans. Inf. Syst., 2014

A Comprehensive Framework for Counterfeit Defect Coverage Analysis and Detection Assessment.

Ujjwal Guin, Daniel DiMase, Mohammad Tehranipoor

J. Electron. Test., 2014

Counterfeit Integrated Circuits: Detection, Avoidance, and the Challenges Ahead.

Ujjwal Guin, Daniel DiMase, Mohammad Tehranipoor

J. Electron. Test., 2014

Cybersecurity Standards: Managing Risk and Creating Resilience.

Zachary A. Collier, Daniel DiMase, Steve Walters, Mark Mohammad Tehranipoor, James H. Lambert, Igor Linkov

Computer, 2014

Identification of testable representative paths for low-cost verification of circuit performance during manufacturing and in-field tests.

Jifeng Chen, LeRoy Winemberg, Mohammad Tehranipoor

Proceedings of the 32nd IEEE VLSI Test Symposium, 2014

Tutorial T4: All You Need to Know about Hardware Trojans and Counterfeit ICs.

Mohammad Tehranipoor, Domenic Forte

Proceedings of the 2014 27th International Conference on VLSI Design, 2014

T1A: Opportunities and challenges for secure hardware and verifying trust in integrated circuits.

Mohammad Tehranipoor, Charles Knapp

Proceedings of the 27th IEEE International System-on-Chip Conference, 2014

CSST: An Efficient Secure Split-Test for Preventing IC Piracy.

Md. Tauhidur Rahman, Domenic Forte, Quihang Shi, Gustavo K. Contreras, Mohammad Tehranipoor

Proceedings of the IEEE 23rd North Atlantic Test Workshop, 2014

On-chip sensor selection for effective speed-binning.

Qihang Shi, Mohammad Tehranipoor, Xiaoxiao Wang, LeRoy Winemberg

Proceedings of the IEEE 57th International Midwest Symposium on Circuits and Systems, 2014

Bit selection algorithm suitable for high-volume production of SRAM-PUF.

Kan Xiao, Md. Tauhidur Rahman, Domenic Forte, Yu Huang, Mei Su, Mohammad Tehranipoor

Proceedings of the 2014 IEEE International Symposium on Hardware-Oriented Security and Trust, 2014

CSST: Preventing distribution of unlicensed and rejected ICs by untrusted foundry and assembly.

Md. Tauhidur Rahman, Domenic Forte, Quihang Shi, Gustavo K. Contreras, Mark Mohammad Tehranipoor

Proceedings of the 2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2014

SAM: A comprehensive mechanism for accessing embedded sensors in modern SoCs.

Miao Tony He, Mohammad Tehranipoor

Proceedings of the 2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2014

Aging analysis for recycled FPGA detection.

Halit Dogan, Domenic Forte, Mark Mohammad Tehranipoor

Proceedings of the 2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2014

ARO-PUF: An aging-resistant ring oscillator PUF design.

Md. Tauhidur Rahman, Domenic Forte, Jim Fahrny, Mohammad Tehranipoor

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

Hacking and protecting IC hardware.

Said Hamdioui, Jean-Luc Danger, Giorgio Di Natale, Fethulah Smailbegovic, Gerard van Battum, Mark M. Tehranipoor

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

TI-TRNG: Technology Independent True Random Number Generator.

Md. Tauhidur Rahman, Kan Xiao, Domenic Forte, Xuhei Zhang, Zhijie Jerry Shi, Mohammad Tehranipoor

Proceedings of the 51st Annual Design Automation Conference 2014, 2014

Low-cost On-Chip Structures for Combating Die and IC Recycling.

Ujjwal Guin, Xuehui Zhang, Domenic Forte, Mohammad Tehranipoor

Proceedings of the 51st Annual Design Automation Conference 2014, 2014

An All Digital Distributed Sensor Network Based Framework for Continuous Noise Monitoring and Timing Failure Analysis in SoCs.

Mehdi Sadi, Zoe Conroy, Bill Eklow, Matthias Kamm, Nematollah Bidokhti, Mark Mohammad Tehranipoor

Proceedings of the 23rd IEEE Asian Test Symposium, 2014

Advanced Analysis of Cell Stability for Reliable SRAM PUFs.

Alison Hosey, Md. Tauhidur Rahman, Kan Xiao, Domenic Forte, Mohammad Tehranipoor

Proceedings of the 23rd IEEE Asian Test Symposium, 2014

Circuit Path Grading Considering Layout, Process Variations, and Cross Talk.

Ke Peng, Mahmut Yilmaz, Mohammad Tehranipoor

Proceedings of the Testing for Small-Delay Defects in Nanoscale CMOS Integrated Circuits., 2014

Faster-than-at-Speed Test for Screening Small-Delay Defects.

Nisar Ahmed, Mohammad Tehranipoor

Proceedings of the Testing for Small-Delay Defects in Nanoscale CMOS Integrated Circuits., 2014

2013

Crosstalk- and Process Variations-Aware High-Quality Tests for Small-Delay Defects.

Ke Peng, Mahmut Yilmaz, Krishnendu Chakrabarty, Mohammad Tehranipoor

IEEE Trans. Very Large Scale Integr. Syst., 2013

Power-safe application of tdf patterns to flip-chip designs during wafer test.

Wei Zhao, Junxia Ma, Mohammad Tehranipoor, Sreejit Chakravarty

ACM Trans. Design Autom. Electr. Syst., 2013

Generation of Effective 1-Detect TDF Patterns for Detecting Small-Delay Defects.

Fang Bao, Ke Peng, Mohammad Tehranipoor, Krishnendu Chakrabarty

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013

Detection of trojans using a combined ring oscillator network and off-chip transient power analysis.

Xuehui Zhang, Andrew Ferraiuolo, Mohammad Tehranipoor

ACM J. Emerg. Technol. Comput. Syst., 2013

Efficient Pattern Generation for Small-Delay Defects Using Selection of Critical Faults.

Fang Bao, Ke Peng, Mahmut Yilmaz, Krishnendu Chakrabarty, LeRoy Winemberg, Mohammad Tehranipoor

J. Electron. Test., 2013

A Clock Sweeping Technique for Detecting Hardware Trojans Impacting Circuits Delay.

Kan Xiao, Xuehui Zhang, Mohammad Tehranipoor

IEEE Des. Test, 2013

A Sensor-Assisted Self-Authentication Framework for Hardware Trojan Detection.

Azadeh Davoodi, Min Li, Mohammad Tehranipoor

IEEE Des. Test, 2013

Protection Against Hardware Trojan Attacks: Towards a Comprehensive Solution.

Swarup Bhunia, Miron Abramovici, Dakshi Agrawal, Paul Bradley, Michael S. Hsiao, Jim Plusquellic, Mohammad Tehranipoor

IEEE Des. Test, 2013

A study on the effectiveness of Trojan detection techniques using a red team blue team approach.

Xuehui Zhang, Kan Xiao, Mohammad Tehranipoor, Jeyavijayan Rajendran, Ramesh Karri

Proceedings of the 31st IEEE VLSI Test Symposium, 2013

Special session 12A: Hot topic counterfeit IC identification: How can test help?

Ilia Polian, Mohammad Tehranipoor

Proceedings of the 31st IEEE VLSI Test Symposium, 2013

Anti-counterfeit Techniques: From Design to Resign.

Ujjwal Guin, Domenic Forte, Mohammad Tehranipoor

Proceedings of the 14th International Workshop on Microprocessor Test and Verification, 2013

A novel flow for reducing clock skew considering NBTI effect and process variations.

Jifeng Chen, Mohammad Tehranipoor

Proceedings of the International Symposium on Quality Electronic Design, 2013

On design vulnerability analysis and trust benchmarks development.

Hassan Salmani, Mohammad Tehranipoor, Ramesh Karri

Proceedings of the 2013 IEEE 31st International Conference on Computer Design, 2013

Functional Fmax test-time reduction using novel DFTs for circuit initialization.

Ujjwal Guin, Tapan J. Chakraborty, Mohammad Tehranipoor

Proceedings of the 2013 IEEE 31st International Conference on Computer Design, 2013

BISA: Built-in self-authentication for preventing hardware Trojan insertion.

Kan Xiao, Mohammad Tehranipoor

Proceedings of the 2013 IEEE International Symposium on Hardware-Oriented Security and Trust, 2013

Analyzing circuit vulnerability to hardware Trojan insertion at the behavioral level.

Hassan Salmani, Mohammad Tehranipoor

Proceedings of the 2013 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2013

Secure Split-Test for preventing IC piracy by untrusted foundry and assembly.

Gustavo K. Contreras, Md. Tauhidur Rahman, Mohammad Tehranipoor

Proceedings of the 2013 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2013

On Achieving Capture Power Safety in At-Speed Scan-Based Logic BIST.

Akihiro Tomita, Xiaoqing Wen, Yasuo Sato, Seiji Kajihara, Patrick Girard, Mohammad Tehranipoor, Laung-Terng Wang

Proceedings of the 22nd Asian Test Symposium, 2013

Critical Paths Selection and Test Cost Reduction Considering Process Variations.

Jifeng Chen, Mohammad Tehranipoor

Proceedings of the 22nd Asian Test Symposium, 2013

Worst-Case Critical-Path Delay Analysis Considering Power-Supply Noise.

Fang Bao, Mohammad Tehranipoor, Harry H. Chen

Proceedings of the 22nd Asian Test Symposium, 2013

2012

Design and Analysis of a Delay Sensor Applicable to Process/Environmental Variations and Aging Measurements.

Xiaoxiao Wang, Mohammad Tehranipoor, Saji George, Dat Tran, LeRoy Winemberg

IEEE Trans. Very Large Scale Integr. Syst., 2012

A Novel Technique for Improving Hardware Trojan Detection and Reducing Trojan Activation Time.

Hassan Salmani, Mohammad Tehranipoor, Jim Plusquellic

IEEE Trans. Very Large Scale Integr. Syst., 2012

Layout-Aware Switching Activity Localization to Enhance Hardware Trojan Detection.

Hassan Salmani, Mohammad Tehranipoor

IEEE Trans. Inf. Forensics Secur., 2012

Ensuring Power-Safe Application of Test Patterns Using an Effective Gating Approach Considering Current Limits.

Wei Zhao, Mohammad Tehranipoor, Sreejit Chakravarty

J. Low Power Electron., 2012

Layout-Aware Pattern Evaluation and Analysis for Power-Safe Application of Transition Delay Fault Patterns.

Hassan Salmani, Wei Zhao, Mohammad Tehranipoor, Sreejit Chakravarty, Patrick Girard, Xiaoqing Wen

J. Low Power Electron., 2012

A Layout-Aware Pattern Grading Procedure for Critical Paths Considering Power Supply Noise and Crosstalk.

Junxia Ma, Mohammad Tehranipoor, Patrick Girard

J. Electron. Test., 2012

A novel method for fast identification of peak current during test.

Wei Zhao, Sreejit Chakravarty, Junxia Ma, Narendra Devta-Prasanna, Fan Yang, Mohammad Tehranipoor

Proceedings of the 30th IEEE VLSI Test Symposium, 2012

On pinpoint capture power management in at-speed scan test generation.

Xiaoqing Wen, Y. Nishida, Kohei Miyase, Seiji Kajihara, Patrick Girard, Mohammad Tehranipoor, Laung-Terng Wang

Proceedings of the 2012 IEEE International Test Conference, 2012

Radic: A standard-cell-based sensor for on-chip aging and flip-flop metastability measurements.

Xiaoxiao Wang, Dat Tran, Saji George, LeRoy Winemberg, Nisar Ahmed, Steve Palosh, Allan Dobin, Mohammad Tehranipoor

Proceedings of the 2012 IEEE International Test Conference, 2012

Representative Critical Reliability Paths for low-cost and accurate on-chip aging evaluation.

Shuo Wang, Jifeng Chen, Mohammad Tehranipoor

Proceedings of the 2012 IEEE/ACM International Conference on Computer-Aided Design, 2012

Experimental analysis of a ring oscillator network for hardware Trojan detection in a 90nm ASIC.

Andrew Ferraiuolo, Xuehui Zhang, Mohammad Tehranipoor

Proceedings of the 2012 IEEE/ACM International Conference on Computer-Aided Design, 2012

TSUNAMI: a light-weight on-chip structure for measuring timing uncertainty induced by noise during functional and test operations.

Shuo Wang, Mohammad Tehranipoor

Proceedings of the Great Lakes Symposium on VLSI 2012, 2012

A zero-overhead IC identification technique using clock sweeping and path delay analysis.

Nicholas Tuzzio, Kan Xiao, Xuehui Zhang, Mohammad Tehranipoor

Proceedings of the Great Lakes Symposium on VLSI 2012, 2012

Efficient selection and analysis of critical-reliability paths and gates.

Jifeng Chen, Shuo Wang, Mohammad Tehranipoor

Proceedings of the Great Lakes Symposium on VLSI 2012, 2012

Path-delay fingerprinting for identification of recovered ICs.

Xuehui Zhang, Kan Xiao, Mohammad Tehranipoor

Proceedings of the 2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2012

Identification of recovered ICs using fingerprints from a light-weight on-chip sensor.

Xuehui Zhang, Nicholas Tuzzio, Mohammad Tehranipoor

Proceedings of the 49th Annual Design Automation Conference 2012, 2012

PowerMAX: Fast Power Analysis during Test.

Wei Zhao, Mohammad Tehranipoor

Proceedings of the 21st IEEE Asian Test Symposium, 2012

2011

An Experimental Analysis of Power and Delay Signal-to-Noise Requirements for Detecting Trojans and Methods for Achieving the Required Detection Sensitivities.

Charles Lamech, Reza M. Rad, Mohammad Tehranipoor, Jim Plusquellic

IEEE Trans. Inf. Forensics Secur., 2011

Layout-Aware Critical Path Delay Test Under Maximum Power Supply Noise Effects.

Junxia Ma, Mohammad Tehranipoor

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011

A Metric to Target Small-Delay Defects in Industrial Circuits.

Mahmut Yilmaz, Mohammad Tehranipoor, Krishnendu Chakrabarty

IEEE Des. Test Comput., 2011

Trustworthy Hardware: Trojan Detection and Design-for-Trust Challenges.

Mohammad Tehranipoor, Hassan Salmani, Xuehui Zhang, Michel Wang, Ramesh Karri, Jeyavijayan Rajendran, Kurt Rosenfeld

Computer, 2011

Power-safe test application using an effective gating approach considering current limits.

Wei Zhao, Mohammad Tehranipoor, Sreejit Chakravarty

Proceedings of the 29th IEEE VLSI Test Symposium, 2011

Special session: Hot topic: Smart silicon.

LeRoy Winemberg, Mohammad Tehranipoor

Proceedings of the 29th IEEE VLSI Test Symposium, 2011

Special session 5B: Panel How much toggle activity should we be testing with?

Xiaoqing Wen, Mohammad Tehranipoor, Rohit Kapur, Anand Bhat, Amitava Majumdar, LeRoy Winemberg

Proceedings of the 29th IEEE VLSI Test Symposium, 2011

Power-aware test generation with guaranteed launch safety for at-speed scan testing.

Xiaoqing Wen, Kazunari Enokimoto, Kohei Miyase, Yuta Yamato, Michael A. Kochte, Seiji Kajihara, Patrick Girard, Mohammad Tehranipoor

Proceedings of the 29th IEEE VLSI Test Symposium, 2011

Case Study: Efficient SDD test generation for very large integrated circuits.

Ke Peng, Fang Bao, Geoff Shofner, LeRoy Winemberg, Mohammad Tehranipoor

Proceedings of the 29th IEEE VLSI Test Symposium, 2011

Low-cost diagnostic pattern generation and evaluation procedures for noise-related failures.

Junxia Ma, Nisar Ahmed, Mohammad Tehranipoor

Proceedings of the 29th IEEE VLSI Test Symposium, 2011

Red team: Design of intelligent hardware trojans with known defense schemes.

Xuehui Zhang, Nicholas Tuzzio, Mohammad Tehranipoor

Proceedings of the IEEE 29th International Conference on Computer Design, 2011

Case study: Detecting hardware Trojans in third-party digital IP cores.

Xuehui Zhang, Mohammad Tehranipoor

Proceedings of the HOST 2011, 2011

Peak power identification on power bumps during test application.

Wei Zhao, Mohammad Tehranipoor

Proceedings of the 2011 International Green Computing Conference and Workshops, 2011

Critical Fault-Based Pattern Generation for Screening SDDs.

Fang Bao, Ke Peng, Mahmut Yilmaz, Krishnendu Chakrabarty, LeRoy Winemberg, Mohammad Tehranipoor

Proceedings of the 16th European Test Symposium, 2011

RON: An on-chip ring oscillator network for hardware Trojan detection.

Xuehui Zhang, Mohammad Tehranipoor

Proceedings of the Design, Automation and Test in Europe, 2011

In-field aging measurement and calibration for power-performance optimization.

Shuo Wang, Mohammad Tehranipoor, LeRoy Winemberg

Proceedings of the 48th Design Automation Conference, 2011

On Generation of 1-Detect TDF Pattern Set with Significantly Increased SDD Coverage.

Fang Bao, Ke Peng, Krishnendu Chakrabarty, Mohammad Tehranipoor

Proceedings of the 20th IEEE Asian Test Symposium, 2011

Test and Diagnosis for Small-Delay Defects.

Mohammad Tehranipoor, Ke Peng, Krishnendu Chakrabarty

Springer, ISBN: 978-1-4419-8296-4, 2011

2010

Hardware Trojan Horses.

Mohammad Tehranipoor, Berk Sunar

Proceedings of the Towards Hardware-Intrinsic Security - Foundations and Practice, 2010

A Sensitivity Analysis of Power Signal Methods for Detecting Hardware Trojans Under Real Process and Environmental Conditions.

Reza M. Rad, James F. Plusquellic, Mohammad Tehranipoor

IEEE Trans. Very Large Scale Integr. Syst., 2010

Test-Pattern Selection for Screening Small-Delay Defects in Very-Deep Submicrometer Integrated Circuits.

Mahmut Yilmaz, Krishnendu Chakrabarty, Mohammad Tehranipoor

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010

A Comprehensive Analysis of Transition Fault Coverage and Test Power Dissipation for Launch-Off-Shift and Launch-Off-Capture Schemes.

Fangmei Wu, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Mohammad Tehranipoor, Xiaoqing Wen, Nisar Ahmed

J. Low Power Electron., 2010

A Novel IR-Drop Tolerant Transition Delay Fault Test Pattern Generation Procedure.

Nisar Ahmed, Mohammad Tehranipoor

J. Low Power Electron., 2010

High Launch Switching Activity Reduction in At-Speed Scan Testing Using CTX: A Clock-Gating-Based Test Relaxation and X-Filling Scheme.

Kohei Miyase, Xiaoqing Wen, Hiroshi Furukawa, Yuta Yamato, Seiji Kajihara, Patrick Girard, Laung-Terng Wang, Mohammad Tehranipoor

IEICE Trans. Inf. Syst., 2010

A Survey of Hardware Trojan Taxonomy and Detection.

Mohammad Tehranipoor, Farinaz Koushanfar

IEEE Des. Test Comput., 2010

Guest Editors' Introduction: Confronting the Hardware Trustworthiness Problem.

Mohammad Tehranipoor, Farinaz Koushanfar

IEEE Des. Test Comput., 2010

Power Supply Noise: A Survey on Effects and Research.

Mohammad Tehranipoor, Kenneth M. Butler

IEEE Des. Test Comput., 2010

Trustworthy Hardware: Identifying and Classifying Hardware Trojans.

Ramesh Karri, Jeyavijayan Rajendran, Kurt Rosenfeld, Mohammad Tehranipoor

Computer, 2010

A layout-aware approach for improving localized switching to detect hardware Trojans in integrated circuits.

Hassan Salmani, Mohammad Tehranipoor, Jim Plusquellic

Proceedings of the 2010 IEEE International Workshop on Information Forensics and Security, 2010

A novel hybrid method for SDD pattern grading and selection.

Ke Peng, Jason Thibodeau, Mahmut Yilmaz, Krishnendu Chakrabarty, Mohammad Tehranipoor

Proceedings of the 28th IEEE VLSI Test Symposium, 2010

Is test power reduction through X-filling good enough?

Fangmei Wu, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Mohammad Tehranipoor, Kohei Miyase, Xiaoqing Wen, Nisar Ahmed

Proceedings of the 2011 IEEE International Test Conference, 2010

Identification of IR-drop hot-spots in defective power distribution network using TDF ATPG.

Junxia Ma, Mohammad Tehranipoor, Ozgur Sinanoglu, Sobeeh Almukhaizim

Proceedings of the 5th International Design and Test Workshop, 2010

Pattern grading for testing critical paths considering power supply noise and crosstalk using a layout-aware quality metric.

Junxia Ma, Jeremy Lee, Mohammad Tehranipoor, Nisar Ahmed, Patrick Girard

Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, 2010

Full-circuit SPICE simulation based validation of dynamic delay estimation.

Ke Peng, Yu Huang, Pinki Mallick, Wu-Tung Cheng, Mohammad Tehranipoor

Proceedings of the 15th European Test Symposium, 2010

Analysis of power consumption and transition fault coverage for LOS and LOC testing schemes.

Fangmei Wu, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Junxia Ma, Wei Zhao, Mohammad Tehranipoor, Xiaoqing Wen

Proceedings of the 13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2010

Novel Physical Unclonable Function with process and environmental variations.

Xiaoxiao Wang, Mohammad Tehranipoor

Proceedings of the Design, Automation and Test in Europe, 2010

High-quality pattern selection for screening small-delay defects considering process variations and crosstalk.

Ke Peng, Mahmut Yilmaz, Mohammad Tehranipoor, Krishnendu Chakrabarty

Proceedings of the Design, Automation and Test in Europe, 2010

Power-Safe Application of Transition Delay Fault Patterns Considering Current Limit during Wafer Test.

Wei Zhao, Junxia Ma, Mohammad Tehranipoor, Sreejit Chakravarty

Proceedings of the 19th IEEE Asian Test Symposium, 2010

A Noise-Aware Hybrid Method for SDD Pattern Grading and Selection.

Ke Peng, Mahmut Yilmaz, Krishnendu Chakrabarty, Mohammad Tehranipoor

Proceedings of the 19th IEEE Asian Test Symposium, 2010

Circuit Topology-Based Test Pattern Generation for Small-Delay Defects.

Sandeep Kumar Goel, Krishnendu Chakrabarty, Mahmut Yilmaz, Ke Peng, Mohammad Tehranipoor

Proceedings of the 19th IEEE Asian Test Symposium, 2010

Emulating and diagnosing IR-drop by using dynamic SDF.

Ke Peng, Yu Huang, Ruifeng Guo, Wu-Tung Cheng, Mohammad Tehranipoor

Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010

2009

A Novel Faster-Than-at-Speed Transition-Delay Test Method Considering IR-Drop Effects.

Nisar Ahmed, Mohammad Tehranipoor

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009

Layout-Aware Pattern Generation for Maximizing Supply Noise Effects on Critical Paths.

Junxia Ma, Jeremy Lee, Mohammad Tehranipoor

Proceedings of the 27th IEEE VLSI Test Symposium, 2009

A novel architecture for on-chip path delay measurement.

Xiaoxiao Wang, Mohammad Tehranipoor, Ramyanshu Datta

Proceedings of the 2009 IEEE International Test Conference, 2009

New Design Strategy for Improving Hardware Trojan Detection and Reducing Trojan Activation Time.

Hassan Salmani, Mohammad Tehranipoor, Jim Plusquellic

Proceedings of the IEEE International Workshop on Hardware-Oriented Security and Trust, 2009

2008

Low-Transition Test Pattern Generation for BIST-Based Applications.

Mehrdad Nourani, Mohammad Tehranipoor, Nisar Ahmed

IEEE Trans. Computers, 2008

Layout-Aware Transition-Delay Fault Pattern Generation with Evenly Distributed Switching Activity.

Jeremy Lee, Mohammad Tehranipoor

J. Low Power Electron., 2008

SCT: A novel approach for testing and configuring nanoscale devices.

Reza M. Rad, Mohammad Tehranipoor

ACM J. Emerg. Technol. Comput. Syst., 2008

Defect Tolerance for Nanoscale Crossbar-Based Devices.

Mohammad Tehranipoor, Reza M. Rad

IEEE Des. Test Comput., 2008

Test-Pattern Grading and Pattern Selection for Small-Delay Defects.

Mahmut Yilmaz, Krishnendu Chakrabarty, Mohammad Tehranipoor

Proceedings of the 26th IEEE VLSI Test Symposium (VTS 2008), April 27, 2008

LS-TDF: Low-Switching Transition Delay Fault Pattern Generation.

Jeremy Lee, Mohammad Tehranipoor

Proceedings of the 26th IEEE VLSI Test Symposium (VTS 2008), April 27, 2008

Interconnect-Aware and Layout-Oriented Test-Pattern Selection for Small-Delay Defects.

Mahmut Yilmaz, Krishnendu Chakrabarty, Mohammad Tehranipoor

Proceedings of the 2008 IEEE International Test Conference, 2008

Power Distribution Failure Analysis Using Transition-Delay Fault Patterns.

Junxia Ma, Jeremy Lee, Mohammad Tehranipoor

Proceedings of the 2008 IEEE International Test Conference, 2008

A Novel Pattern Generation Framework for Inducing Maximum Crosstalk Effects on Delay-Sensitive Paths.

Jeremy Lee, Mohammad Tehranipoor

Proceedings of the 2008 IEEE International Test Conference, 2008

Path-RO: a novel on-chip critical path delay measurement under process variations.

Xiaoxiao Wang, Mohammad Tehranipoor, Ramyanshu Datta

Proceedings of the 2008 International Conference on Computer-Aided Design, 2008

Power supply signal calibration techniques for improving detection resolution to hardware Trojans.

Reza M. Rad, Xiaoxiao Wang, Mohammad Tehranipoor, Jim Plusquellic

Proceedings of the 2008 International Conference on Computer-Aided Design, 2008

Detecting Malicious Inclusions in Secure Hardware: Challenges and Solutions.

Xiaoxiao Wang, Mohammad Tehranipoor, Jim Plusquellic

Proceedings of the IEEE International Workshop on Hardware-Oriented Security and Trust, 2008

Sensitivity Analysis to Hardware Trojans using Power Supply Transient Signals.

Reza M. Rad, Jim Plusquellic, Mohammad Tehranipoor

Proceedings of the IEEE International Workshop on Hardware-Oriented Security and Trust, 2008

Hardware Trojan Detection and Isolation Using Current Integration and Localized Current Analysis.

Xiaoxiao Wang, Hassan Salmani, Mohammad Tehranipoor, James F. Plusquellic

Proceedings of the 23rd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2008), 2008

Layout-Aware, IR-Drop Tolerant Transition Fault Pattern Generation.

Jeremy Lee, Sumit Narayan, Mike Kapralos, Mohammad Tehranipoor

Proceedings of the Design, Automation and Test in Europe, 2008

CTX: A Clock-Gating-Based Test Relaxation and X-Filling Scheme for Reducing Yield Loss Risk in At-Speed Scan Testing.

Hiroshi Furukawa, Xiaoqing Wen, Kohei Miyase, Yuta Yamato, Seiji Kajihara, Patrick Girard, Laung-Terng Wang, Mohammad Tehranipoor

Proceedings of the 17th IEEE Asian Test Symposium, 2008

2007

A critical-path-aware partial gating approach for test power reduction.

Mohammed ElShoukry, Mohammad Tehranipoor, C. P. Ravikumar

ACM Trans. Design Autom. Electr. Syst., 2007

Securing Designs against Scan-Based Side-Channel Attacks.

Jeremy Lee, Mohammad Tehranipoor, Chintan Patel, Jim Plusquellic

IEEE Trans. Dependable Secur. Comput., 2007

Built-In Self-Test and Recovery Procedures for Molecular Electronics-Based Nanofabrics.

Mohammad Tehranipoor, Reza M. Rad

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007

Local At-Speed Scan Enable Generation for Transition Fault Testing Using Low-Cost Testers.

Nisar Ahmed, Mohammad Tehranipoor, C. P. Ravikumar, Kenneth M. Butler

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007

Evaluating area and performance of hybrid FPGAs with nanoscale clusters and CMOS routing.

Reza M. Rad, Mohammad Tehranipoor

ACM J. Emerg. Technol. Comput. Syst., 2007

Guest Editorial.

Mohammad Tehranipoor

J. Electron. Test., 2007

Guest Editors' Introduction: IR Drop in Very Deep-Submicron Designs.

Mohammad Tehranipoor, Kenneth M. Butler

IEEE Des. Test Comput., 2007

Supply Voltage Noise Aware ATPG for Transition Delay Faults.

Nisar Ahmed, Mohammad Tehranipoor, Vinay Jayaram

Proceedings of the 25th IEEE VLSI Test Symposium (VTS 2007), 2007

Transition Delay Fault Test Pattern Generation Considering Supply Voltage Noise in a SOC Design.

Nisar Ahmed, Mohammad Tehranipoor, Vinay Jayaram

Proceedings of the 44th Design Automation Conference, 2007

2006

Quiescent-Signal Analysis: A Multiple Supply Pad IDDQ Method.

Jim Plusquellic, Dhruva Acharyya, Abhishek Singh, Mohammad Tehranipoor, Chintan Patel

IEEE Des. Test Comput., 2006

Improving Transition Delay Test Using a Hybrid Method.

Nisar Ahmed, Mohammad Tehranipoor

IEEE Des. Test Comput., 2006

SCT: An Approach For Testing and Configuring Nanoscale Devices.

Reza M. Rad, Mohammad Tehranipoor

Proceedings of the 24th IEEE VLSI Test Symposium (VTS 2006), 30 April, 2006

A Low-Cost Solution for Protecting IPs Against Scan-Based Side-Channel Attacks.

Jeremy Lee, Mohammad Tehranipoor, Jim Plusquellic

Proceedings of the 24th IEEE VLSI Test Symposium (VTS 2006), 30 April, 2006

Session Abstract.

Kee Sup Kim, Mohammad Tehranipoor

Proceedings of the 24th IEEE VLSI Test Symposium (VTS 2006), 30 April, 2006

A novel framework for faster-than-at-speed delay test considering IR-drop effects.

Nisar Ahmed, Mohammad Tehranipoor, Vinay Jayaram

Proceedings of the 2006 International Conference on Computer-Aided Design, 2006

Test and recovery for fine-grained nanoscale architectures.

Mohammad Tehranipoor, Reza M. Rad

Proceedings of the ACM/SIGDA 14th International Symposium on Field Programmable Gate Arrays, 2006

Fine-grained island style architecture for molecular electronic devices.

Mohammad Tehranipoor, Reza M. Rad

Proceedings of the ACM/SIGDA 14th International Symposium on Field Programmable Gate Arrays, 2006

A Reconfiguration-based Defect Tolerance Method for Nanoscale Devices.

Reza M. Rad, Mohammad Tehranipoor

Proceedings of the 21th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2006), 2006

A new hybrid FPGA with nanoscale clusters and CMOS routing.

Reza M. Rad, Mohammad Tehranipoor

Proceedings of the 43rd Design Automation Conference, 2006

Timing-based delay test for screening small delay defects.

Nisar Ahmed, Mohammad Tehranipoor, Vinay Jayaram

Proceedings of the 43rd Design Automation Conference, 2006

2005

Nine-coded compression technique for testing embedded cores in SoCs.

Mohammad Tehranipoor, Mehrdad Nourani, Krishnendu Chakrabarty

IEEE Trans. Very Large Scale Integr. Syst., 2005

Pattern Generation and Estimation for Power Supply Noise Analysis.

Mehrdad Nourani, Mohammad Tehranipoor, Nisar Ahmed

Proceedings of the 23rd IEEE VLSI Test Symposium (VTS 2005), 2005

At-Speed Transition Fault Testing With Low Speed Scan Enable.

Nisar Ahmed, C. P. Ravikumar, Mohammad Tehranipoor, Jim Plusquellic

Proceedings of the 23rd IEEE VLSI Test Symposium (VTS 2005), 2005

Enhanced launch-off-capture transition fault testing.

Nisar Ahmed, Mohammad Tehranipoor, C. P. Ravikumar

Proceedings of the Proceedings 2005 IEEE International Test Conference, 2005

Defect Tolerance for Molecular Electronics-Based NanoFabrics Using Built-In Self-Test Procedure.

Mohammad Tehranipoor

Proceedings of the 20th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2005), 2005

Securing Scan Design Using Lock and Key Technique.

Jeremy Lee, Mohammad Tehranipoor, Chintan Patel, Jim Plusquellic

Proceedings of the 20th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2005), 2005

Improving Transition Delay Fault Coverage Using Hybrid Scan-Based Technique.

Nisar Ahmed, Mohammad Tehranipoor

Proceedings of the 20th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2005), 2005

Low Transition LFSR for BIST-Based Applications.

Mohammad Tehranipoor, Mehrdad Nourani, Nisar Ahmed

Proceedings of the 14th Asian Test Symposium (ATS 2005), 2005

Partial Gating Optimization for Power Reduction During Test Application.

Mohammed ElShoukry, Mohammad Tehranipoor, C. P. Ravikumar

Proceedings of the 14th Asian Test Symposium (ATS 2005), 2005