Mark Kassab

According to our database, Mark Kassab authored at least 46 papers between 1995 and 2022.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2022

Efficient Test Compression Configuration Selection.

Chong-Siao Ye, Shi-Xuan Zheng, Fong-Jyun Tsai, Chen Wang, Kuen-Jong Lee, Wu-Tung Cheng, Sudhakar M. Reddy, Justyna Zawada, Mark Kassab, Janusz Rajski

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

Accurate Estimation of Test Pattern Counts for a Wide-Range of EDT Input/Output Channel Configurations.

Shi-Xuan Zheng, Chung-Yu Yeh, Kuen-Jong Lee, Chen Wang, Wu-Tung Cheng, Mark Kassab, Janusz Rajski, Sudhakar M. Reddy

Proceedings of the 40th IEEE VLSI Test Symposium, 2022

2020

Effective Design of Layout-Friendly EDT Decompressor.

Yu Huang, Janusz Rajski, Mark Kassab, Nilanjan Mukherjee, Jeffrey Mayer

Proceedings of the 38th IEEE VLSI Test Symposium, 2020

Prediction of Test Pattern Count and Test Data Volume for Scan Architectures under Different Input Channel Configurations.

Fong-Jyun Tsai, Chong-Siao Ye, Kuen-Jong Lee, Shi-Xuan Zheng, Yu Huang, Wu-Tung Cheng, Sudhakar M. Reddy, Mark Kassab, Janusz Rajski, Chen Wang, Justyna Zawada

Proceedings of the IEEE International Test Conference, 2020

Streaming Scan Network (SSN): An Efficient Packetized Data Network for Testing of Complex SoCs.

Jean-François Côté, Mark Kassab, Wojciech Janiszewski, Ricardo Rodrigues, Reinhard Meier, Bartosz Kaczmarek, Peter Orlando, Geir Eide, Janusz Rajski, Glenn Colón-Bonet, Naveen Mysore, Ya Yin, Pankaj Pant

Proceedings of the IEEE International Test Conference, 2020

Estimation of Test Data Volume for Scan Architectures with Different Numbers of Input Channels.

Fong-Jyun Tsai, Chong-Siao Ye, Yu Huang, Kuen-Jong Lee, Wu-Tung Cheng, Sudhakar M. Reddy, Mark Kassab, Janusz Rajski, Shi-Xuan Zheng

Proceedings of the IEEE International Test Conference in Asia, 2020

Efficient Prognostication of Pattern Count with Different Input Compression Ratios.

Fong-Jyun Tsai, Chong-Siao Ye, Yu Huang, Kuen-Jong Lee, Wu-Tung Cheng, Sudhakar M. Reddy, Mark Kassab, Janusz Rajski

Proceedings of the IEEE European Test Symposium, 2020

2019

TEA: A Test Generation Algorithm for Designs with Timing Exceptions.

Naixing Wang, Chen Wang, Kun-Han Tsai, Wu-Tung Cheng, Xijiang Lin, Mark Kassab, Irith Pomeranz

Proceedings of the 28th IEEE Asian Test Symposium, 2019

2015

Scan Test Bandwidth Management for Ultralarge-Scale System-on-Chip Architectures.

Wu-Tung Cheng, Yan Dong, Grady Giles, Yu Huang, Jakub Janicki, Mark Kassab, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer

IEEE Trans. Very Large Scale Integr. Syst., 2015

Isometric Test Data Compression.

Amit Kumar, Mark Kassab, Elham K. Moghaddam, Nilanjan Mukherjee, Janusz Rajski, Sudhakar M. Reddy, Jerzy Tyszer, Chen Wang

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015

Hybrid Hierarchical and Modular Tests for SoC Designs.

Guoliang Li, Jun Qian, Qinfu Yang, Yuan Zuo, Rui Li, Yu Huang, Mark Kassab, Janusz Rajski

Proceedings of the 24th IEEE North Atlantic Test Workshop, 2015

2014

Erratum to "Test Time Reduction in EDT Bandwidth Management for SoC Designs".

Jakub Janicki, Mark Kassab, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014

Test Compression Improvement with EDT Channel Sharing in SoC Designs.

Yu Huang, Mark Kassab, Jay Jahangiri, Janusz Rajski, Wu-Tung Cheng, Dongkwan Han, Jihye Kim, Kun Young Chung

Proceedings of the IEEE 23rd North Atlantic Test Workshop, 2014

Isometric test compression with low toggling activity.

Amit Kumar, Mark Kassab, Elham K. Moghaddam, Nilanjan Mukherjee, Janusz Rajski, Sudhakar M. Reddy, Jerzy Tyszer, Chen Wang

Proceedings of the 2014 International Test Conference, 2014

Using dynamic shift to reduce test data volume in high-compression designs.

Xijiang Lin, Mark Kassab, Janusz Rajski

Proceedings of the 19th IEEE European Test Symposium, 2014

Timing-Aware ATPG.

Mark Kassab, Benoit Nadeau-Dostie, Xijiang Lin

Proceedings of the Testing for Small-Delay Defects in Nanoscale CMOS Integrated Circuits., 2014

2013

Test Time Reduction in EDT Bandwidth Management for SoC Designs.

Jakub Janicki, Mark Kassab, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013

EDT bandwidth management - Practical scenarios for large SoC designs.

Jakub Janicki, Jerzy Tyszer, Wu-Tung Cheng, Yu Huang, Mark Kassab, Nilanjan Mukherjee, Janusz Rajski, Yan Dong, Grady Giles

Proceedings of the 2013 IEEE International Test Conference, 2013

2012

EDT Bandwidth Management in SoC Designs.

Jakub Janicki, Mark Kassab, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012

2011

A novel Test Access Mechanism for failure diagnosis of multiple isolated identical cores.

Manish Sharma, Avijit Dutta, Wu-Tung Cheng, Brady Benware, Mark Kassab

Proceedings of the 2011 IEEE International Test Conference, 2011

EDT channel bandwidth management in SoC designs with pattern-independent test access mechanism.

Jakub Janicki, Jerzy Tyszer, Avijit Dutta, Mark Kassab, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski

Proceedings of the 2011 IEEE International Test Conference, 2011

2010

At-speed scan test with low switching activity.

Elham K. Moghaddam, Janusz Rajski, Sudhakar M. Reddy, Mark Kassab

Proceedings of the 28th IEEE VLSI Test Symposium, 2010

Clock control architecture and ATPG for reducing pattern count in SoC designs with multiple clock domains.

Tom Waayers, Richard Morren, Xijiang Lin, Mark Kassab

Proceedings of the 2011 IEEE International Test Conference, 2010

Low capture power at-speed test in EDT environment.

Elham K. Moghaddam, Janusz Rajski, Sudhakar M. Reddy, Xijiang Lin, Nilanjan Mukherjee, Mark Kassab

Proceedings of the 2011 IEEE International Test Conference, 2010

Dynamic channel allocation for higher EDT compression in SoC designs.

Mark Kassab, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Jakub Janicki, Jerzy Tyszer

Proceedings of the 2011 IEEE International Test Conference, 2010

2009

Low-Power Scan Operation in Test Compression Environment.

Dariusz Czysz, Mark Kassab, Xijiang Lin, Grzegorz Mrugalski, Janusz Rajski, Jerzy Tyszer

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009

Test Generation for Designs with On-Chip Clock Generators.

Xijiang Lin, Mark Kassab

Proceedings of the Eighteentgh Asian Test Symposium, 2009

2008

X-Press: Two-Stage X-Tolerant Compactor With Programmable Selector.

Janusz Rajski, Jerzy Tyszer, Grzegorz Mrugalski, Wu-Tung Cheng, Nilanjan Mukherjee, Mark Kassab

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008

Low Power Scan Shift and Capture in the EDT Environment.

Dariusz Czysz, Mark Kassab, Xijiang Lin, Grzegorz Mrugalski, Janusz Rajski, Jerzy Tyszer

Proceedings of the 2008 IEEE International Test Conference, 2008

2007

X-Tolerant Compactor with On-Chip Registration and Signature-Based Diagnosis.

Jerzy Tyszer, Janusz Rajski, Grzegorz Mrugalski, Nilanjan Mukherjee, Mark Kassab, Wu-Tung Cheng, Manish Sharma, Liyang Lai

IEEE Des. Test Comput., 2007

Test Generation in the Presence of Timing Exceptions and Constraints.

Dhiraj Goswami, Kun-Han Tsai, Mark Kassab, Janusz Rajski

Proceedings of the 44th Design Automation Conference, 2007

Test Generation for Timing-Critical Transition Faults.

Xijiang Lin, Mark Kassab, Janusz Rajski

Proceedings of the 16th Asian Test Symposium, 2007

2006

X-Press Compactor for 1000x Reduction of Test Data.

Janusz Rajski, Jerzy Tyszer, Grzegorz Mrugalski, Wu-Tung Cheng, Nilanjan Mukherjee, Mark Kassab

Proceedings of the 2006 IEEE International Test Conference, 2006

OCI: Open Compression Interface.

Bruce Cory, Rohit Kapur, Mick Tegethoff, Mark Kassab, Brion L. Keller, Kee Sup Kim, Dwayne Burek, Steven F. Oakland, Benoit Nadeau-Dostie

Proceedings of the 2006 IEEE International Test Conference, 2006

Timing-Aware ATPG for High Quality At-speed Testing of Small Delay Defects.

Xijiang Lin, Kun-Han Tsai, Chen Wang, Mark Kassab, Janusz Rajski, Takeo Kobayashi, Randy Klingenberg, Yasuo Sato, Shuji Hamada, Takashi Aikyo

Proceedings of the 15th Asian Test Symposium, 2006

At-Speed Testing with Timing Exceptions and Constraints-Case Studies.

Dhiraj Goswami, Kun-Han Tsai, Mark Kassab, Takeo Kobayashi, Janusz Rajski, Bruce Swanson, Darryl Walters, Yasuo Sato, Toshiharu Asaka, Takashi Aikyo

Proceedings of the 15th Asian Test Symposium, 2006

2004

Embedded deterministic test.

Janusz Rajski, Jerzy Tyszer, Mark Kassab, Nilanjan Mukherjee

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004

Realizing High Test Quality Goals with Smart Test Resource Usage.

Xinli Gu, Cyndee Wang, Abby Lee, Bill Eklow, Kun-Han Tsai, Jan Arild Tofte, Mark Kassab, Janusz Rajski

Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004

Affordable and Effective Screening of Delay Defects in ASICs using the Inline Resistance Fault Model.

Brady Benware, Cam Lu, John Van Slyke, Prabhu Krishnamurthy, Robert Madge, Martin Keim, Mark Kassab, Janusz Rajski

Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004

2003

Embedded Deterministic Test for Low-Cost Manufacturing.

Janusz Rajski, Mark Kassab, Nilanjan Mukherjee, Nagesh Tamarapalli, Jerzy Tyszer, Jun Qian

IEEE Des. Test Comput., 2003

Industrial Experience with Adoption of EDT for Low-Cost Test without Concessions.

Frank Poehl, Matthias Beck, Ralf Arnold, Peter Muhmenthaler, Nagesh Tamarapalli, Mark Kassab, Nilanjan Mukherjee, Janusz Rajski

Proceedings of the Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September, 2003

2002

Embedded Deterministic Test for Low-Cost Manufacturing Test.

Janusz Rajski, Jerzy Tyszer, Mark Kassab, Nilanjan Mukherjee, Rob Thompson, Kun-Han Tsai, Andre Hertwig, Nagesh Tamarapalli, Grzegorz Mrugalski, Geir Eide, Jun Qian

Proceedings of the Proceedings IEEE International Test Conference 2002, 2002

1999

Logic BIST for large industrial designs: real issues and case studies.

Graham Hetherington, Tony Fryars, Nagesh Tamarapalli, Mark Kassab, Abu S. M. Hassan, Janusz Rajski

Proceedings of the Proceedings IEEE International Test Conference 1999, 1999

1998

A Fast Sequential Learning Technique for Real Circuits with Application to Enhancing ATPG Performance.

Aiman H. El-Maleh, Mark Kassab, Janusz Rajski

Proceedings of the 35th Conference on Design Automation, 1998

1995

Hierarchical Functional-Fault Simulation for High-Level Synthesis.

Mark Kassab, Janusz Rajski, Jerzy Tyszer

Proceedings of the Proceedings IEEE International Test Conference 1995, 1995

Software Accelerated Functional Fault Simulation for Data-Path Architectures.

Mark Kassab, Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer

Proceedings of the 32st Conference on Design Automation, 1995