Mark H. Pearce

According to our database, Mark H. Pearce authored at least 3 papers between 1997 and 2003.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2003

A 2× load/store pipe for a low-power 1-GHz embedded processor.

Zongjian Chen, Daniel Murray, Steve Nishimoto, Mark H. Pearce, Max Oyker, Daniel Rodriguez, Robert Rogenmoser, Dongwook (Drew) Suh, Erik Supnet, Vincent von Kaenel, George Yiu

IEEE J. Solid State Circuits, 2003

1998

A low-cost, 300-MHz, RISC CPU with attached media processor.

Sribalan Santhanam, Allen J. Baum, David Bertucci, Mike Braganza, Kevin Broch, Todd Broch, James Burnette, Edward Chang, Kwong-Tak Chui, Dan Dobberpuhl, Paul M. Donahue, Joel Grodstein, Insung Kim, Daniel Murray, Mark H. Pearce, Amy Silveria, Dave Souydalay, Aaron Spink, Robert Stepanian, Anand Varadharajan, Vincent R. von Kaenel, Ricky Wen

IEEE J. Solid State Circuits, 1998

1997

A 160-MHz, 32-b, 0.5-W CMOS RISC Microprocessor.

James Montanaro, Richard T. Witek, Krishna Anne, Andrew J. Black, Elizabeth M. Cooper, Daniel W. Dobberpuhl, Paul M. Donahue, Jim Eno, Gregory W. Hoeppner, David Kruckemyer, Thomas H. Lee, Peter C. M. Lin, Liam Madden, Daniel Murray, Mark H. Pearce, Sribalan Santhanam, Kathryn J. Snyder, Ray Stephany, Stephen C. Thierauf

Digit. Tech. J., 1997