Mark Chen
Affiliations:- Taiwan Semiconductor Manufacturing Company, Hsinchu, Taiwan
According to our database1,
Mark Chen
authored at least 9 papers
between 2016 and 2020.
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Bibliography
2020
Embedded PLL Phase Noise Measurement Based on a PFD/CP MASH 1-1-1 ΔΣ Time-to-Digital Converter in 7nm CMOS.
Proceedings of the IEEE Symposium on VLSI Circuits, 2020
2019
A 0.85mm<sup>2</sup> 51%-Efficient 11-dBm Compact DCO-DPA in 16-nm FinFET for Sub-Gigahertz IoT TX Using HD<sub>2</sub> Self-Suppression and Pulling Mitigation.
IEEE J. Solid State Circuits, 2019
A 387.6fs Integrated Jitter and -80dBc Reference Spurs Ring based PLL with Track- and-Hold Charge Pump and Automatic Loop Gain Control in 7nm FinFET CMOS.
Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019
A 77/79-GHz Frequency Generator in 16-nm CMOS for FMCW Radar Applications Based on a 26-GHz Oscillator with Co-Generated Third Harmonic.
Proceedings of the 45th IEEE European Solid State Circuits Conference, 2019
2018
An All-Digital PLL for Cellular Mobile Phones in 28-nm CMOS with -55 dBc Fractional and -91 dBc Reference Spurs.
IEEE Trans. Circuits Syst. I Regul. Pap., 2018
A Digital Bang-Bang Phase-Locked Loop with Background Injection Timing Calibration and Automatic Loop Gain Control in 7NM FinFET CMOS.
Proceedings of the 2018 IEEE Symposium on VLSI Circuits, 2018
2017
19.6 A 0.2V trifilar-coil DCO with DC-DC converter in 16nm FinFET CMOS with 188dB FOM, 1.3kHz resolution, and frequency pushing of 38MHz/V for energy harvesting applications.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017
A 0.031mm<sup>2</sup>, 910fs, 0.5-4GHz injection type SOC PLL with 90dB built-in supply noise rejection in 10nm FinFET CMOS.
Proceedings of the 2017 IEEE Custom Integrated Circuits Conference, 2017
2016
A 0.034mm<sup>2</sup>, 725fs RMS jitter, 1.8%/V frequency-pushing, 10.8-19.3GHz transformer-based fractional-N all-digital PLL in 10nm FinFET CMOS.
Proceedings of the 2016 IEEE Symposium on VLSI Circuits, 2016