Mark A. Indovina

Orcid: 0000-0002-6645-4596

According to our database1, Mark A. Indovina authored at least 14 papers between 2006 and 2024.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Bibliography

2024
ReApprox-PIM: Reconfigurable Approximate Lookup-Table (LUT)-Based Processing-in-Memory (PIM) Machine Learning Accelerator.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., August, 2024

3DL-PIM: A Look-Up Table Oriented Programmable Processing in Memory Architecture Based on the 3-D Stacked Memory for Data-Intensive Applications.
IEEE Trans. Emerg. Top. Comput., 2024

2023
CNNET: A Configurable Hardware Accelerator for Efficient Inference of 8-bit Fixed-Point CNNs.
Proceedings of the 36th IEEE International System-on-Chip Conference, 2023

FlutPIM: : A Look-up Table-based Processing in Memory Architecture with Floating-point Computation Support for Deep Learning Applications.
Proceedings of the Great Lakes Symposium on VLSI 2023, 2023

2022
Look-up-Table Based Processing-in-Memory Architecture With Programmable Precision-Scaling for Deep Learning Applications.
IEEE Trans. Parallel Distributed Syst., 2022

Implementation and Evaluation of Deep Neural Networks in Commercially Available Processing in Memory Hardware.
Proceedings of the 35th IEEE International System-on-Chip Conference, 2022

POLAR: Performance-aware On-device Learning Capable Programmable Processing-in-Memory Architecture for Low-Power ML Applications.
Proceedings of the 25th Euromicro Conference on Digital System Design, 2022

2021
Flexible Instruction Set Architecture for Programmable Look-up Table based Processing-in-Memory.
Proceedings of the 39th IEEE International Conference on Computer Design, 2021

2020
pPIM: A Programmable Processor-in-Memory Architecture With Precision-Scaling for Deep Learning.
IEEE Comput. Archit. Lett., 2020

The IANET Hardware Accelerator for Audio and Visual Data Classification.
Proceedings of the 33rd IEEE International System-on-Chip Conference, 2020

2018
Testing WiNoC-Enabled Multicore Chips with BIST for Wireless Interconnects.
Proceedings of the Twelfth IEEE/ACM International Symposium on Networks-on-Chip, 2018

A 0.24pJ/bit, 16Gbps OOK Transmitter Circuit in 45-nm CMOS for Inter and Intra-Chip Wireless Interconnects.
Proceedings of the 2018 on Great Lakes Symposium on VLSI, 2018

2017
A 0.36pJ/bit, 17Gbps OOK receiver in 45-nm CMOS for inter and intra-chip wireless interconnects.
Proceedings of the 30th IEEE International System-on-Chip Conference, 2017

2006
Industrially proving the SPIRIT consortium specifications for design chain integration.
Proceedings of the Conference on Design, Automation and Test in Europe: Designers' Forum, 2006


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