Marius Meyer

According to our database, Marius Meyer authored at least 7 papers between 2020 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2024

HiHiSpMV: Sparse Matrix Vector Multiplication with Hierarchical Row Reductions on FPGAs with High Bandwidth Memory.

Abdul Rehman Tareen, Marius Meyer, Christian Plessl, Tobias Kenter

Proceedings of the 32nd IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2024

Optimizing Communication for Latency Sensitive HPC Applications on up to 48 FPGAs Using ACCL.

Marius Meyer, Tobias Kenter, Lucian Petrica, Kenneth O'Brien, Michaela Blott, Christian Plessl

Proceedings of the Euro-Par 2024: Parallel Processing, 2024

2023

Multi-FPGA Designs and Scaling of HPC Challenge Benchmarks via MPI and Circuit-switched Inter-FPGA Networks.

Marius Meyer, Tobias Kenter, Christian Plessl

ACM Trans. Reconfigurable Technol. Syst., June, 2023

2022

In-depth FPGA accelerator performance evaluation with single node benchmarks from the HPC challenge benchmark suite for Intel and Xilinx FPGAs using OpenCL.

Marius Meyer, Tobias Kenter, Christian Plessl

J. Parallel Distributed Comput., 2022

2021

Towards Performance Characterization of FPGAs in Context of HPC using OpenCL Benchmarks.

Marius Meyer

Proceedings of the HEART '21: 11th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies, 2021

2020

Evaluating FPGA Accelerator Performance with a Parameterized OpenCL Adaptation of the HPCChallenge Benchmark Suite.

Marius Meyer, Tobias Kenter, Christian Plessl

CoRR, 2020

Evaluating FPGA Accelerator Performance with a Parameterized OpenCL Adaptation of Selected Benchmarks of the HPCChallenge Benchmark Suite.

Marius Meyer, Tobias Kenter, Christian Plessl

Proceedings of the 2020 IEEE/ACM International Workshop on Heterogeneous High-performance Reconfigurable Computing, 2020