Marisa López-Vallejo

IEEE Trans. Parallel Distributed Syst., 2016

SPICE Compact Modeling of Bipolar/Unipolar Memristor Switching Governed by Electrical Thresholds.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2016

Reliable design methodology: The combined effect of radiation, variability and temperature.

[BibT_eX]

[DOI]

Hernan Aparicio

Proceedings of the 13th International Conference on Synthesis, 2016

A temperature-independent PUF with a configurable duty cycle of CMOS ring oscillators.

[BibT_eX]

[DOI]

Javier Agustin

Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

2015

Implementation of a Real-Time Spectrum Analyzer on FPGA Platforms.

[BibT_eX]

[DOI]

Victor Iglesias

Jesús Grajal

IEEE Trans. Instrum. Meas., 2015

An In-Depth Analysis of Ring Oscillators: Exploiting Their Configurable Duty-Cycle.

[BibT_eX]

[DOI]

Javier Agustin

IEEE Trans. Circuits Syst. I Regul. Pap., 2015

Real-time low-complexity automatic modulation classifier for pulsed radar signals.

[BibT_eX]

[DOI]

Victor Iglesias

Jesús Grajal

Pablo Royer

Omar A. Yeste Ojeda

IEEE Trans. Aerosp. Electron. Syst., 2015

Evolution of radiation-induced soft errors in FinFET SRAMs under process variations beyond 22nm.

[BibT_eX]

[DOI]

Pablo Royer

Proceedings of the 2015 IEEE/ACM International Symposium on Nanoscale Architectures, 2015

A thermal adaptive scheme for reliable write operation on RRAM based architectures.

[BibT_eX]

[DOI]

Proceedings of the 33rd IEEE International Conference on Computer Design, 2015

A Dual-Layer Fault Manager for systems based on Xilinx Virtex FPGAs.

[BibT_eX]

[DOI]

Ignacio Herrera-Alzu

C. Gil Soriano

Proceedings of the 2015 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2015

2014

A Self-Timed Multipurpose Delay Sensor for Field Programmable Gate Arrays (FPGAs).

[BibT_eX]

[DOI]

Carlos Gómez Osuna

Sensors, 2014

2013

High Performance FPGA-oriented Mersenne Twister Uniform Random Number Generator.

[BibT_eX]

[DOI]

J. Signal Process. Syst., 2013

Floating-Point Exponentiation Units for Reconfigurable Computing.

[BibT_eX]

[DOI]

ACM Trans. Reconfigurable Technol. Syst., 2013

A 0.0016 mm<sup>2</sup> 0.64 nJ Leakage-Based CMOS Temperature Sensor.

[BibT_eX]

[DOI]

Sensors, 2013

A low power 6t-SRAM using negative bit-line for variability tolerance beyond 22nm node.

[BibT_eX]

[DOI]

Pablo Royer

Proceedings of the Great Lakes Symposium on VLSI 2013 (part of ECRC), 2013

A Low-Area Reference-Free Power Supply Sensor.

[BibT_eX]

[DOI]

Carlos Benito

Proceedings of the 2013 Euromicro Conference on Digital System Design, 2013

2012

Hardware Reuse Improvement through the Domain Specific Language dHDL.

[BibT_eX]

[DOI]

Miguel Angel Sánchez

Proceedings of the 10th IEEE International Symposium on Parallel and Distributed Processing with Applications, 2012

A monitoring infrastructure for FPGA self-awareness and dynamic adaptation.

[BibT_eX]

[DOI]

Carlos Gómez Osuna

Proceedings of the 19th IEEE International Conference on Electronics, Circuits and Systems, 2012

Improving Hardware Reuse through XML-based Interface Encapsulation.

[BibT_eX]

[DOI]

Miguel Angel Sánchez

Proceedings of the 17th IEEE International Conference on Engineering of Complex Computer Systems, 2012

2011

Customizing floating-point units for FPGAs: Area-performance-standard trade-offs.

[BibT_eX]

[DOI]

Microprocess. Microsystems, 2011

Self-reference Scrubber for TMR Systems Based on Xilinx Virtex FPGAs.

[BibT_eX]

[DOI]

Ignacio Herrera-Alzu

Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation, 2011

Real time FPGA implementation of an automatic modulation classifier for electronic warfare applications.

[BibT_eX]

[DOI]

Proceedings of the 19th European Signal Processing Conference, 2011

On-chip Monitoring: A Light-Weight Interconnection Network Approach.

[BibT_eX]

[DOI]

Carlos Gómez Osuna

Proceedings of the 14th Euromicro Conference on Digital System Design, 2011

2010

Thermal analysis and modeling of embedded processors.

[BibT_eX]

[DOI]

Cándido Méndez

Comput. Electr. Eng., 2010

2009

Exploring performance-power trade-offs for look-up tables in SRAM-based FPGAs.

[BibT_eX]

[DOI]

Walter Bolognesi

Pedro Echeverría Aramendi

Proceedings of the 16th IEEE International Conference on Electronics, 2009

SoC Communication Architectures: From Interconnection Buses to Packet-Switched NoCs.

[BibT_eX]

[DOI]

Proceedings of the Embedded Systems Design and Verification, 2009

2008

Power Considerations in Banked CAMs: A Leakage Reduction Approach.

[BibT_eX]

[DOI]

VLSI Design, 2008

Joint hardware-software leakage minimization approach for the register file of VLIW embedded architectures.

[BibT_eX]

[DOI]

Integr., 2008

A hardware mechanism to reduce the energy consumption of the register file of in-order architectures.

[BibT_eX]

[DOI]

Alexander V. Veidenbaum

Int. J. Embed. Syst., 2008

Experimental methodology for power characterization of FPGAs.

[BibT_eX]

[DOI]

Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, 2008

Variance reduction techniques for Monte Carlo simulations. A parameterizable FPGA approach.

[BibT_eX]

[DOI]

Jose María Pesquero

Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, 2008

A Web-Based Environment Providing Remote Access To FPGA Platforms For Teaching Digital Hardware Design.

[BibT_eX]

Angel Fernandez Herrero

Ignacio Elguezábal

Proceedings of the IADIS International Conference e-Learning 2008, 2008

Designing Highly Parameterized Hardware using xHdl.

[BibT_eX]

[DOI]

Proceedings of the Forum on specification and Design Languages, 2008

An FPGA run-time parameterisable Log-Normal Random Number Generator.

[BibT_eX]

[DOI]

Proceedings of the Reconfigurable Computing: Architectures, 2008

2007

Energy-aware compilation and hardware design for VLIW embedded systems.

[BibT_eX]

[DOI]

Int. J. Embed. Syst., 2007

Reduction of Register File Delay Due to Process Variability in VLIW Embedded Processors.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

Leakage-based On-Chip Thermal Sensor for CMOS Technology.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

Joint Source-Channel Decoding ASIP Architecture for Sensor Networks.

[BibT_eX]

[DOI]

Proceedings of the Embedded Software and Systems, [Third] International Conference, 2007

Thermal Characterization and Thermal Management in Processor-Based Systems.

[BibT_eX]

[DOI]

Proceedings of the Power-aware Computing Systems, 21.01. - 26.01.2007, 2007

2006

Target Independent Thermal Modeling for Embedded Processors.

[BibT_eX]

[DOI]

Cándido Méndez

Proceedings of the International Symposium on Industrial Embedded Systems, 2006

Compiler-Driven Leakage Energy Reduction in Banked Register Files.

[BibT_eX]

[DOI]

Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2006

Leakage Energy Reduction in Banked Content Addressable Memories.

[BibT_eX]

[DOI]

Proceedings of the 13th IEEE International Conference on Electronics, 2006

Analysis of the Thermal Impact of Source-Code Transformations in Embedded-Processors.

[BibT_eX]

[DOI]

Cándido Méndez

Proceedings of the 13th IEEE International Conference on Electronics, 2006

Automated design space exploration of FPGA-based FFT architectures based on area and power estimation.

[BibT_eX]

[DOI]

Mario Garrido

Proceedings of the 2006 IEEE International Conference on Field Programmable Technology, 2006

New Schemes in Clustered VLIW Processors Applied to Turbo Decoding.

[BibT_eX]

[DOI]

Proceedings of the 2006 IEEE International Conference on Application-Specific Systems, 2006

2005

State-of-the-Art SoC Communication Architectures.

[BibT_eX]

[DOI]

Proceedings of the Embedded Systems Handbook., 2005

Integrating functional and power simulation in embedded systems design.

[BibT_eX]

[DOI]

J. Embed. Comput., 2005

Compiler-Driven Power Optimizations in the Register File of Processor-Based Systems.

[BibT_eX]

[DOI]

Proceedings of the Power-aware Computing Systems, 3.-8. April 2005, 2005

2004

Improving IP core reuse through the application of the meta-language xHDL.

[BibT_eX]

[DOI]

Marcos M. A. Sanchez

Fernandez Herrero

Proceedings of the Forum on specification and Design Languages, 2004

2003

On the hardware-software partitioning problem: System modeling and partitioning techniques.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2003

Power-Aware Compilation for Register File Energy Reduction.

[BibT_eX]

[DOI]

Alexander V. Veidenbaum

Int. J. Parallel Program., 2003

A Unified Framework for Power-Aware Design of Embedded Systems.

[BibT_eX]

[DOI]

Proceedings of the Integrated Circuit and System Design, 2003

An Efficient Hash Table Based Approach to Avoid State Space Explosion in History Driven Quasi-Static Scheduling.

[BibT_eX]

[DOI]

Antonio G. Lomeña

Yosinori Watanabe

Alex Kondratyev

Proceedings of the 2003 Design, 2003

Energy Aware Register File Implementation through Instruction Predecode.

[BibT_eX]

[DOI]

Alexander V. Veidenbaum

Carlos A. Lopez

Proceedings of the 14th IEEE International Conference on Application-Specific Systems, 2003

State Space Compression in History Driven Quasi-Static Scheduling.

[BibT_eX]

[DOI]

Proceedings of the Embedded Software for SoC, 2003

2002

Block processing technique for low power turbo decoder design.

[BibT_eX]

[DOI]

Inkyu Lee

Syed Aon Mujtaba

Proceedings of the 55th IEEE Vehicular Technology Conference, 2002

2001

ED68K. A design framework for the development of digital systems based on MC68000.

[BibT_eX]

J. M. Fernández Freire

J. Colás

Proceedings of the Computers and Education. Towards an Interconnected Society, 2001

2000

Constraint-Driven System Partitioning.

[BibT_eX]

[DOI]

Jesús Grajal

Proceedings of the 2000 Design, 2000

1999

Hardware-Software Partitioning at the Knowledge Level.

[BibT_eX]

[DOI]

Natividad Martínez Madrid

Appl. Intell., 1999

1998

Hardware-Software Prototyping from LOTOS.

[BibT_eX]

[DOI]

Luis Sánchez Fernández

Gernot Koch

María Luisa López Vallejo

Carlos Delgado Kloos

Wolfgang Rosenstiel

Des. Autom. Embed. Syst., 1998

Applying the Propose&Revise Strategy to the Hardware-Software Partitioning Problem.

[BibT_eX]

[DOI]

Proceedings of the Methodology and Tools in Knowledge-Based Systems, 1998

A Knowledge-based System for Hardware-Software Partitioning.

[BibT_eX]

[DOI]

Proceedings of the 1998 Design, 1998

1996

A Co-Design Methodology Based on Formal Specification and High-level Estimation.

[BibT_eX]

[DOI]

Carlos Carreras