Marios Kleanthous
Orcid: 0009-0009-8877-8581
According to our database1,
Marios Kleanthous
authored at least 14 papers
between 2008 and 2024.
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Bibliography
2024
Agile C-states: A Core C-state Architecture for Latency Critical Applications Optimizing both Transition and Cold-Start Latency.
ACM Trans. Archit. Code Optim., December, 2024
2019
ACM Trans. Archit. Code Optim., 2019
2018
An energy-efficient and error-resilient server ecosystem exceeding conservative scaling limits.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018
2016
IEEE Comput. Archit. Lett., 2016
2015
Modeling the implications of DRAM failures and protection techniques on datacenter TCO.
Proceedings of the 48th International Symposium on Microarchitecture, 2015
Proceedings of the 2015 IEEE International Symposium on Performance Analysis of Systems and Software, 2015
2014
Int. J. Interdiscip. Telecommun. Netw., 2014
2013
Implicit-storing and redundant-encoding-of-attribute information in error-correction-codes.
Proceedings of the 46th Annual IEEE/ACM International Symposium on Microarchitecture, 2013
Proceedings of the 2012 IEEE International Symposium on Performance Analysis of Systems & Software, 2013
2011
Trans. High Perform. Embed. Archit. Compil., 2011
CATCH: A mechanism for dynamically detecting cache-content-duplication in instruction caches.
ACM Trans. Archit. Code Optim., 2011
2010
2008
Proceedings of the High Performance Embedded Architectures and Compilers, 2008
CATCH: A Mechanism for Dynamically Detecting Cache-Content-Duplication and its Application to Instruction Caches.
Proceedings of the Design, Automation and Test in Europe, 2008