Marios C. Papaefthymiou

CoRR, 2018

A 0.23mW Heterogeneous Deep-Learning Processor Supporting Dynamic Execution of Conditional Neural Networks.

[BibT_eX]

[DOI]

Hsi-Shou Wu

Proceedings of the 44th IEEE European Solid State Circuits Conference, 2018

2017

20.7 A 13.8µW binaural dual-microphone digital ANSI S1.11 filter bank for hearing aids with zero-short-circuit-current logic in 65nm CMOS.

[BibT_eX]

[DOI]

Hsi-Shou Wu

Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017

A 1.25pJ/bit 0.048mm2 AES core with DPA resistance for IoT devices.

[BibT_eX]

[DOI]

Shengshuo Lu

Proceedings of the IEEE Asian Solid-State Circuits Conference, 2017

2016

Design Methodology for Synthesizing Resonant Clock Networks in the Presence of Dynamic Voltage/Frequency Scaling.

[BibT_eX]

[DOI]

Seyong Ahn

Minseok Kang

Taewhan Kim

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016

A 5.5GHz 0.84TOPS/mm2 neural network engine with stream architecture and resonant clock mesh.

[BibT_eX]

[DOI]

Shengshuo Lu

Proceedings of the IEEE Asian Solid-State Circuits Conference, 2016

2015

1.32GHz high-throughput charge-recovery AES core with resistance to DPA attacks.

[BibT_eX]

[DOI]

Shengshuo Lu

Proceedings of the Symposium on VLSI Circuits, 2015

A 934MHz 9Gb/s 3.2pJ/b/iteration charge-recovery LDPC decoder with in-package inductors.

[BibT_eX]

[DOI]

Tai-Chuan Ou

Proceedings of the IEEE Asian Solid-State Circuits Conference, 2015

Synthesis of resonant clock networks supporting dynamic voltage / frequency scaling.

[BibT_eX]

[DOI]

Seyong Ahn

Minseok Kang

Taewhan Kim

Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015

2014

27.6 An 821MHz 7.9Gb/s 7.3pJ/b/iteration charge-recovery LDPC decoder.

[BibT_eX]

[DOI]

Tai-Chuan Ou

Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014

2013

Designing for Responsiveness with Computational Sprinting.

[BibT_eX]

[DOI]

Yixin Luo

Anuj Chandawalla

IEEE Micro, 2013

Utilizing Dark Silicon to Save Energy with Computational Sprinting.

[BibT_eX]

[DOI]

Laurel Emurian

Lei Shao

IEEE Micro, 2013

Resonant-Clock Design for a Power-Efficient, High-Volume x86-64 Microprocessor.

[BibT_eX]

[DOI]

Samuel Naffziger

IEEE J. Solid State Circuits, 2013

Computational sprinting on a hardware/software testbed.

[BibT_eX]

[DOI]

Laurel Emurian

Lei Shao

Proceedings of the Architectural Support for Programming Languages and Operating Systems, 2013

2012

Energy-Efficient Low-Latency 600 MHz FIR With High-Overdrive Charge-Recovery Logic.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2012

Computational sprinting.

[BibT_eX]

[DOI]

Yixin Luo

Anuj Chandawalla

Proceedings of the 18th IEEE International Symposium on High Performance Computer Architecture, 2012

2011

A 5.5GS/s 28mW 5-bit flash ADC with resonant clock distribution.

[BibT_eX]

[DOI]

Proceedings of the 37th European Solid-State Circuits Conference, 2011

2010

187 MHz Subthreshold-Supply Charge-Recovery FIR.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2010

2009

A charge-recovery 600MHz FIR filter with 1.5-cycle latency overhead.

[BibT_eX]

[DOI]

Proceedings of the 35th European Solid-State Circuits Conference, 2009

A resonant-clock 200MHz ARM926EJ-STM microcontroller.

[BibT_eX]

[DOI]

Alexander T. Ishii

Proceedings of the 35th European Solid-State Circuits Conference, 2009

2008

Resonant-Clock Latch-Based Design.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2008

2007

A Multi-Mode Power Gating Structure for Low-Voltage Deep-Submicron CMOS ICs.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2007

Energy-Efficient GHz-Class Charge-Recovery Logic.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2007

Skew spreading for peak current reduction.

[BibT_eX]

[DOI]

Zhengtao Yu

Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, 2007

A 0.8-1.2GHz Single-Phase Resonant-Clocked FIR Filter with Level-Sensitive Latches.

[BibT_eX]

[DOI]

Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, 2007

2006

Practical repeater insertion for low power: what repeater library do we need?

[BibT_eX]

[DOI]

Yuantao Peng

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

Parallelizing post-placement timing optimization.

[BibT_eX]

[DOI]

Jiyoun Kim

José Luis Neves

Proceedings of the 20th International Parallel and Distributed Processing Symposium (IPDPS 2006), 2006

900MHz to 1.2GHz Two-Phase Resonant Clock Network with Programmable Driver and Loading.

[BibT_eX]

[DOI]

Proceedings of the IEEE 2006 Custom Integrated Circuits Conference, 2006

2005

HyPE: hybrid power estimation for IP-based systems-on-chip.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005

Charge-Recovery Computing on Silicon.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2005

Multi-Session Partitioning for Parallel Timing Optimization.

[BibT_eX]

[DOI]

Jiyoun Kim

José Neves

Proceedings of the Sixth International Conference on Parallel and Distributed Computing, 2005

Boost Logic: A High Speed Energy Recovery Circuit Family.

[BibT_eX]

[DOI]

Proceedings of the 2005 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2005), 2005

Two-Phase Resonant Clock Distribution.

[BibT_eX]

[DOI]

Proceedings of the 2005 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2005), 2005

A GHz-class charge recovery logic.

[BibT_eX]

[DOI]

Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005

RIP: An Efficient Hybrid Repeater Insertion Scheme for Low Power.

[BibT_eX]

[DOI]

Yuantao Peng

Proceedings of the 2005 Design, 2005

Fast, efficient, recovering, and irreversible.

[BibT_eX]

[DOI]

Proceedings of the Second Conference on Computing Frontiers, 2005

2004

A Markov chain sequence generator for power macromodeling.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004

Clock tree layout design for reduced delay uncertainty.

[BibT_eX]

[DOI]

Dimitrios Velenis

Proceedings of the Proceedings 2004 IEEE International SOC Conference, 2004

A synchronous interface for SoCs with multiple clock domains.

[BibT_eX]

[DOI]

Stephen V. Kosonocky

Proceedings of the Proceedings 2004 IEEE International SOC Conference, 2004

Experimental Evaluation of Resonant Clock Distribution.

[BibT_eX]

[DOI]

Proceedings of the 2004 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2004), 2004

Constant-load energy recovery memory for efficient high-speed operation.

[BibT_eX]

[DOI]

Proceedings of the 2004 International Symposium on Low Power Electronics and Design, 2004

Empirical evaluation of timing and power in resonant clock distribution.

[BibT_eX]

Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

An Algorithm for Geometric Load Balancing with Two Constraints.

[BibT_eX]

[DOI]

Jiyoun Kim

Athar B. Tayyab

Proceedings of the 18th International Parallel and Distributed Processing Symposium (IPDPS 2004), 2004

2003

Design of a 20-mb/s 256-state Viterbi decoder.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2003

A true single-phase energy-recovery multiplier.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2003

Block-based multiperiod dynamic memory design for low data-retention power.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2003

Fine-grain real-time reconfigurable pipelining.

[BibT_eX]

[DOI]

IBM J. Res. Dev., 2003

Energy Recovering ASIC Design.

[BibT_eX]

[DOI]

Proceedings of the 2003 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2003), 2003

A 225 MHz resonant clocked ASIC chip.

[BibT_eX]

[DOI]

Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003

Reduced Delay Uncertainty in High Performance Clock Distribution Networks.

[BibT_eX]

[DOI]

Dimitrios Velenis

Proceedings of the 2003 Design, 2003

HyPE: hybrid power estimation for IP-based programmable systems.

[BibT_eX]

[DOI]

Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003

2002

Retiming and clock scheduling for digital circuit optimization.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002

Energy recovering static memory.

[BibT_eX]

[DOI]

Proceedings of the 2002 International Symposium on Low Power Electronics and Design, 2002

Incorporation of input glitches into power macromodeling.

[BibT_eX]

[DOI]

Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

Design of a high-throughput low-power IS95 Viterbi decoder.

[BibT_eX]

[DOI]

Proceedings of the 39th Design Automation Conference, 2002

2001

True single-phase adiabatic circuitry.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2001

Symbolic debugging of embedded hardware and software.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001

A resonant clock generator for single-phase adiabatic systems.

[BibT_eX]

[DOI]

Proceedings of the 2001 International Symposium on Low Power Electronics and Design, 2001

A clock tree topology extraction algorithm for improving the tolerance of clock distribution networks to delay uncertainty.

[BibT_eX]

[DOI]

Dimitrios Velenis

Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

A static power estimation methodolodgy for IP-based design.

[BibT_eX]

[DOI]

Proceedings of the Conference on Design, Automation and Test in Europe, 2001

A True Single-Phase 8-bit Adiabatic Multiplier.

[BibT_eX]

[DOI]

Proceedings of the 38th Design Automation Conference, 2001

Design, Verification, and Test of a True Single-Phase 8-bit Adiabatic Multiplier.

[BibT_eX]

[DOI]

Proceedings of the 19th Conference on Advanced Research in VLSI (ARVLSI 2001), 2001

2000

Optimizing computations for effective block-processing.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2000

Dynamic Memory Design for Low Data-Retention Power.

[BibT_eX]

[DOI]

Proceedings of the Integrated Circuit Design, 2000

Symbolic debugging of globally optimized behavioral specifications.

[BibT_eX]

[DOI]

Inki Hong

Darko Kirovski

Proceedings of ASP-DAC 2000, 2000

1999

Efficient Block Scheduling to Minimize Context Switching Time for Programmable Embedded Processors.

[BibT_eX]

[DOI]

Inki Hong

Des. Autom. Embed. Syst., 1999

Single-phase source-coupled adiabatic logic.

[BibT_eX]

[DOI]

Proceedings of the 1999 International Symposium on Low Power Electronics and Design, 1999

Analytical macromodeling for high-level power estimation.

[BibT_eX]

[DOI]

Giuseppe Bernacchia

Proceedings of the 1999 IEEE/ACM International Conference on Computer-Aided Design, 1999

Minimizing Sensitivity to Delay Variations in High-Performance Synchronous Circuits.

[BibT_eX]

[DOI]

Proceedings of the 1999 Design, 1999

Maximizing Performance by Retiming and Clock Skew Scheduling.

[BibT_eX]

[DOI]

Proceedings of the 36th Conference on Design Automation, 1999

1998

True single-phase energy-recovering logic for low-power, high-speed VLSI.

[BibT_eX]

[DOI]

Proceedings of the 1998 International Symposium on Low Power Electronics and Design, 1998

Asymptotically efficient retiming under setup and hold constraints.

[BibT_eX]

[DOI]

Proceedings of the 1998 IEEE/ACM International Conference on Computer-Aided Design, 1998

1997

Retiming edge-triggered circuits under general delay models.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1997

Optimizing two-phase, level-clocked circuitry.

[BibT_eX]

[DOI]

Alexander T. Ishii

Charles E. Leiserson

J. ACM, 1997

Computing Strictly-Second Shortest Paths.

[BibT_eX]

[DOI]

Inf. Process. Lett., 1997

Performance Evaluation of Gang Scheduling for Parallel and Distributed Multiprogramming.

[BibT_eX]

[DOI]

Proceedings of the Job Scheduling Strategies for Parallel Processing, 1997

1996

Stochastic Analysis of Gang Scheduling in Parallel and Distributed Systems.

[BibT_eX]

Perform. Evaluation, 1996

An Analysis of Gang Scheduling for Multiprogrammed Parallel Computing Environments.

[BibT_eX]

[DOI]

Proceedings of the 8th Annual ACM Symposium on Parallel Algorithms and Architectures, 1996

A Gang Scheduling Design for Multiprogrammed Parallel Computing Environments.

[BibT_eX]

[DOI]

Hubertus Franke

Pratap Pattnaik

Larry Rudolph

Proceedings of the Job Scheduling Strategies for Parallel Processing, 1996

Fixed-phase retiming for low power design.

[BibT_eX]

[DOI]

Proceedings of the 1996 International Symposium on Low Power Electronics and Design, 1996

Optimizing Systems for Effective Block-Processing: The k-Delay Problem.

[BibT_eX]

[DOI]

Proceedings of the 33st Conference on Design Automation, 1996

1995

DELAY: An Efficient Tool for Retiming with Realistic Delay Modeling.

[BibT_eX]

[DOI]

Proceedings of the 32st Conference on Design Automation, 1995

Efficient retiming under a general delay model.

[BibT_eX]

[DOI]

Proceedings of the 16th Conference on Advanced Research in VLSI (ARVLSI '95), 1995

1994

Precomputation-based sequential logic optimization for low power.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 1994

Understanding Retiming Through Maximum Avarage-Delay Cycles.

[BibT_eX]

[DOI]

Christoforos N. Hadjicostis

Math. Syst. Theory, 1994

Memory Assignment for Multiprocessor Caches through Grey Coloring.

[BibT_eX]

[DOI]

Anant Agarwal

John V. Guttag

Proceedings of the PARLE '94: Parallel Architectures and Languages Europe, 1994

Implementing parallel shortest-paths algorithms.

[BibT_eX]

[DOI]

Joseph Rodrigue

Proceedings of the Parallel Algorithms, 1994

1993

TIM: A Timing Package for Two-Phase, Level-Clocked Circuitry.

[BibT_eX]

[DOI]

Keith H. Randall

Proceedings of the 30th Design Automation Conference. Dallas, 1993

1991

Understanding Retiming Through Maximum Average-Weight Cycles.

[BibT_eX]

[DOI]